From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1FhYZg-0005yD-51 for qemu-devel@nongnu.org; Sat, 20 May 2006 17:01:24 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1FhYZf-0005xj-43 for qemu-devel@nongnu.org; Sat, 20 May 2006 17:01:23 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1FhYZe-0005xc-Sk for qemu-devel@nongnu.org; Sat, 20 May 2006 17:01:22 -0400 Received: from [147.11.1.11] (helo=mail.wrs.com) by monty-python.gnu.org with esmtp (Exim 4.52) id 1FhYdG-0003vR-QL for qemu-devel@nongnu.org; Sat, 20 May 2006 17:05:07 -0400 Received: from ala-mail04.corp.ad.wrs.com (ala-mail04 [147.11.57.145]) by mail.wrs.com (8.13.6/8.13.3) with ESMTP id k4KL1LA5024273 for ; Sat, 20 May 2006 14:01:21 -0700 (PDT) Message-ID: <446F83A0.4000205@windriver.com> Date: Sat, 20 May 2006 16:01:20 -0500 From: Jason Wessel MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------040409050504060702080800" Subject: [Qemu-devel] [PATCH 2/5] PPC Breakpoints for gdb-stub Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. --------------040409050504060702080800 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit This patch adds breakpoint and single stepping support for PPC via the gdb stub. signed-off-by: jason.wessel@windriver.com Jason. --------------040409050504060702080800 Content-Type: text/plain; name="ppc_breakpoints.patch" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="ppc_breakpoints.patch" Index: qemu/target-ppc/translate.c =================================================================== --- qemu.orig/target-ppc/translate.c +++ qemu/target-ppc/translate.c @@ -148,6 +148,7 @@ typedef struct DisasContext { #endif int fpu_enabled; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ + int singlestep_enabled; } DisasContext; struct opc_handler_t { @@ -1738,10 +1739,14 @@ static inline void gen_goto_tb(DisasCont gen_op_set_T1(dest); gen_op_b_T1(); gen_op_set_T0((long)tb + n); + if (ctx->singlestep_enabled) + gen_op_debug(); gen_op_exit_tb(); } else { gen_op_set_T1(dest); gen_op_b_T1(); + if (ctx->singlestep_enabled) + gen_op_debug(); gen_op_set_T0(0); gen_op_exit_tb(); } @@ -2520,12 +2525,22 @@ int gen_intermediate_code_internal (CPUS ctx.mem_idx = ((1 - msr_pr) << 1) | msr_le; #endif ctx.fpu_enabled = msr_fp; + ctx.singlestep_enabled = env->singlestep_enabled; #if defined (DO_SINGLE_STEP) && 0 /* Single step trace mode */ msr_se = 1; #endif /* Set env in case of segfault during code fetch */ while (ctx.exception == EXCP_NONE && gen_opc_ptr < gen_opc_end) { + if (env->nb_breakpoints > 0) { + for(j = 0; j < env->nb_breakpoints; j++) { + if (env->breakpoints[j] == ctx.nip) { + gen_op_update_nip(ctx.nip); + gen_op_debug(); + break; + } + } + } if (search_pc) { j = gen_opc_ptr - gen_opc_buf; if (lj < j) { @@ -2616,8 +2631,12 @@ int gen_intermediate_code_internal (CPUS ctx.exception != EXCP_TRAP)) { RET_EXCP(ctxp, EXCP_TRACE, 0); } - /* if we reach a page boundary, stop generation */ - if ((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) { + + /* if we reach a page boundary or are single stepping, stop + * generation + */ + if (((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || + (env->singlestep_enabled)) { break; } #if defined (DO_SINGLE_STEP) Index: qemu/target-ppc/op.c =================================================================== --- qemu.orig/target-ppc/op.c +++ qemu/target-ppc/op.c @@ -204,6 +204,11 @@ PPC_OP(update_nip) env->nip = PARAM(1); } +PPC_OP(debug) +{ + do_raise_exception(EXCP_DEBUG); +} + /* Segment registers load and store with immediate index */ PPC_OP(load_srin) { --------------040409050504060702080800--