From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 80A05C43334 for ; Thu, 14 Jul 2022 10:29:13 +0000 (UTC) Received: from localhost ([::1]:52784 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oBw5o-0004ap-BW for qemu-devel@archiver.kernel.org; Thu, 14 Jul 2022 06:29:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36142) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oBw4G-0003Wo-6R; Thu, 14 Jul 2022 06:27:36 -0400 Received: from gloria.sntech.de ([185.11.138.130]:42832) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oBw4C-0001d0-Ey; Thu, 14 Jul 2022 06:27:35 -0400 Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1oBw43-00037f-Di; Thu, 14 Jul 2022 12:27:23 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: qemu-devel@nongnu.org Cc: Alistair Francis , Atish Patra , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org, frank.chang@sifive.com, Atish Patra Subject: Re: [PATCH v10 11/12] hw/riscv: virt: Add PMU DT node to the device tree Date: Thu, 14 Jul 2022 12:27:22 +0200 Message-ID: <4485024.MHq7AAxBmi@diego> In-Reply-To: <20220620231603.2547260-12-atishp@rivosinc.com> References: <20220620231603.2547260-1-atishp@rivosinc.com> <20220620231603.2547260-12-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Received-SPF: pass client-ip=185.11.138.130; envelope-from=heiko@sntech.de; helo=gloria.sntech.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Atish, Am Dienstag, 21. Juni 2022, 01:16:01 CEST schrieb Atish Patra: > Qemu virt machine can support few cache events and cycle/instret counters. > It also supports counter overflow for these events. > > Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine > capabilities. There are some dummy nodes added for testing as well. > > Acked-by: Alistair Francis > Signed-off-by: Atish Patra > Signed-off-by: Atish Patra > --- > +static void create_fdt_socket_pmu(RISCVVirtState *s, > + int socket, uint32_t *phandle, > + uint32_t *intc_phandles) > +{ > + int cpu; > + char *pmu_name; > + uint32_t *pmu_cells; > + MachineState *mc = MACHINE(s); > + RISCVCPU hart = s->soc[socket].harts[0]; > + > + pmu_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); > + > + for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { > + pmu_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); > + pmu_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_PMU_OVF); > + } > + > + pmu_name = g_strdup_printf("/soc/pmu"); > + qemu_fdt_add_subnode(mc->fdt, pmu_name); > + qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu"); Where is the binding document for this? As the comment below states the "riscv,event-to-mhpmcounters" property is opensbi-specific and gets removed in the opensbi stage, but that still leaves the pmu node in it and from the version I found, Rob wasn't overly happy with the compatible [0]. Did this get addressed? Thanks Heiko [0] https://lore.kernel.org/all/YXhPqfpXh1VZN07T@robh.at.kernel.org/ > + riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name); > + > + g_free(pmu_name); > + g_free(pmu_cells); > +} > + > static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, > bool is_32_bit, uint32_t *phandle, > uint32_t *irq_mmio_phandle, > @@ -759,6 +786,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, > &intc_phandles[phandle_pos]); > } > } > + create_fdt_socket_pmu(s, socket, phandle, intc_phandles); > } > > if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 7d9e2aca12a9..69bbd9fff4e1 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1110,6 +1110,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) > ISA_EDATA_ENTRY(zve64f, ext_zve64f), > ISA_EDATA_ENTRY(zhinx, ext_zhinx), > ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin), > + ISA_EDATA_ENTRY(sscofpmf, ext_sscofpmf), > ISA_EDATA_ENTRY(svinval, ext_svinval), > ISA_EDATA_ENTRY(svnapot, ext_svnapot), > ISA_EDATA_ENTRY(svpbmt, ext_svpbmt), > diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c > index 34096941c0ce..59feb3c243dd 100644 > --- a/target/riscv/pmu.c > +++ b/target/riscv/pmu.c > @@ -20,11 +20,68 @@ > #include "cpu.h" > #include "pmu.h" > #include "sysemu/cpu-timers.h" > +#include "sysemu/device_tree.h" > > #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ > #define MAKE_32BIT_MASK(shift, length) \ > (((uint32_t)(~0UL) >> (32 - (length))) << (shift)) > > +/** > + * To keep it simple, any event can be mapped to any programmable counters in > + * QEMU. The generic cycle & instruction count events can also be monitored > + * using programmable counters. In that case, mcycle & minstret must continue > + * to provide the correct value as well. Heterogeneous PMU per hart is not > + * supported yet. Thus, number of counters are same across all harts. > + */ > +void riscv_pmu_generate_fdt_node(void *fdt, int num_ctrs, char *pmu_name) > +{ > + uint32_t fdt_event_ctr_map[20] = {}; > + uint32_t cmask; > + > + /* All the programmable counters can map to any event */ > + cmask = MAKE_32BIT_MASK(3, num_ctrs); > + > + /** > + * The event encoding is specified in the SBI specification > + * Event idx is a 20bits wide number encoded as follows: > + * event_idx[19:16] = type > + * event_idx[15:0] = code > + * The code field in cache events are encoded as follows: > + * event_idx.code[15:3] = cache_id > + * event_idx.code[2:1] = op_id > + * event_idx.code[0:0] = result_id > + */ > + > + /* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */ > + fdt_event_ctr_map[0] = cpu_to_be32(0x00000001); > + fdt_event_ctr_map[1] = cpu_to_be32(0x00000001); > + fdt_event_ctr_map[2] = cpu_to_be32(cmask | 1 << 0); > + > + /* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */ > + fdt_event_ctr_map[3] = cpu_to_be32(0x00000002); > + fdt_event_ctr_map[4] = cpu_to_be32(0x00000002); > + fdt_event_ctr_map[5] = cpu_to_be32(cmask | 1 << 2); > + > + /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */ > + fdt_event_ctr_map[6] = cpu_to_be32(0x00010019); > + fdt_event_ctr_map[7] = cpu_to_be32(0x00010019); > + fdt_event_ctr_map[8] = cpu_to_be32(cmask); > + > + /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */ > + fdt_event_ctr_map[9] = cpu_to_be32(0x0001001B); > + fdt_event_ctr_map[10] = cpu_to_be32(0x0001001B); > + fdt_event_ctr_map[11] = cpu_to_be32(cmask); > + > + /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */ > + fdt_event_ctr_map[12] = cpu_to_be32(0x00010021); > + fdt_event_ctr_map[13] = cpu_to_be32(0x00010021); > + fdt_event_ctr_map[14] = cpu_to_be32(cmask); > + > + /* This a OpenSBI specific DT property documented in OpenSBI docs */ > + qemu_fdt_setprop(fdt, pmu_name, "riscv,event-to-mhpmcounters", > + fdt_event_ctr_map, sizeof(fdt_event_ctr_map)); > +} > + > static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx) > { > if (ctr_idx < 3 || ctr_idx >= RV_MAX_MHPMCOUNTERS || > diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h > index 036653627f78..3004ce37b636 100644 > --- a/target/riscv/pmu.h > +++ b/target/riscv/pmu.h > @@ -31,5 +31,6 @@ int riscv_pmu_init(RISCVCPU *cpu, int num_counters); > int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, > uint32_t ctr_idx); > int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx); > +void riscv_pmu_generate_fdt_node(void *fdt, int num_counters, char *pmu_name); > int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, > uint32_t ctr_idx); >