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[174.21.75.75]) by smtp.gmail.com with ESMTPSA id nn2sm14823342pjb.34.2021.10.30.16.52.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 30 Oct 2021 16:52:22 -0700 (PDT) Subject: Re: [PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles To: =?UTF-8?B?RnLDqWTDqXJpYyBQw6l0cm90?= , qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20211025122818.168890-1-frederic.petrot@univ-grenoble-alpes.fr> <20211025122818.168890-7-frederic.petrot@univ-grenoble-alpes.fr> From: Richard Henderson Message-ID: <4490be43-a321-0ca8-9718-445f42deeef5@linaro.org> Date: Sat, 30 Oct 2021 16:52:20 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20211025122818.168890-7-frederic.petrot@univ-grenoble-alpes.fr> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.426, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: philmd@redhat.com, bin.meng@windriver.com, alistair.francis@wdc.com, palmer@dabbelt.com, fabien.portas@grenoble-inp.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/25/21 5:28 AM, Frédéric Pétrot wrote: > This patch is kind of a mess because several files have to be slightly > modified to allow for a new target. In the current status, we have done > our best to have RV64 and RV128 under the same RV64 umbrella, but there > is still work to do to have a single executable for both. > > Once this patch applied, adding risc128-sofmmu to --target-list produces > a (no so useful yet) executable. > > Signed-off-by: Frédéric Pétrot > Co-authored-by: Fabien Portas > --- > configs/devices/riscv128-softmmu/default.mak | 17 +++++++++++++++ > configs/targets/riscv128-softmmu.mak | 5 +++++ > include/disas/dis-asm.h | 1 + > include/hw/riscv/sifive_cpu.h | 3 +++ > target/riscv/cpu-param.h | 5 +++++ > target/riscv/cpu.h | 3 +++ > disas/riscv.c | 5 +++++ > target/riscv/cpu.c | 22 ++++++++++++++++++-- > target/riscv/gdbstub.c | 8 +++++++ > target/riscv/insn_trans/trans_rvd.c.inc | 12 +++++------ > target/riscv/insn_trans/trans_rvf.c.inc | 6 +++--- > target/riscv/Kconfig | 3 +++ > 12 files changed, 79 insertions(+), 11 deletions(-) > create mode 100644 configs/devices/riscv128-softmmu/default.mak > create mode 100644 configs/targets/riscv128-softmmu.mak Can we start with adding -cpu rv128 to the existing riscv64-softmmu executable, before we go so far as to add yet another executable? r~