From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1FuXfn-0000rV-6p for qemu-devel@nongnu.org; Sun, 25 Jun 2006 12:41:23 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1FuXfm-0000qh-AB for qemu-devel@nongnu.org; Sun, 25 Jun 2006 12:41:22 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1FuXfm-0000qe-5D for qemu-devel@nongnu.org; Sun, 25 Jun 2006 12:41:22 -0400 Received: from [84.96.92.55] (helo=smtP.neuf.fr) by monty-python.gnu.org with esmtp (Exim 4.52) id 1FuXrS-0006rb-M6 for qemu-devel@nongnu.org; Sun, 25 Jun 2006 12:53:26 -0400 Received: from [84.102.211.103] by sp604004mt.gpm.neuf.ld (Sun Java System Messaging Server 6.2-5.05 (built Feb 16 2006)) with ESMTP id <0J1F002Z6CXYPJE0@sp604004mt.gpm.neuf.ld> for qemu-devel@nongnu.org; Sun, 25 Jun 2006 18:39:34 +0200 (CEST) Date: Sun, 25 Jun 2006 18:39:21 +0200 From: Fabrice Bellard Subject: Re: [Qemu-devel] Pending MIPS patches In-reply-to: <449EB5FA.6070405@gmail.com> Message-id: <449EBC39.3050701@bellard.org> MIME-version: 1.0 Content-type: text/plain; charset=us-ascii; format=flowed Content-transfer-encoding: 7BIT References: <449EB5FA.6070405@gmail.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Dirk Behme wrote: > Hi, > > just fyi below my list of pending MIPS patches. Not sure if all patches > are ready for inclusion, but maybe they are helpful for somebody. I try > to track which patches are already applied and which not. Please feel > free to add, comment, discuss etc anything. > > Best regards > > Dirk > > Pending MIPS patches (bugs & improvements): > =========================================== > > 1. [PATCH] Huge TLB performance improvement > http://lists.gnu.org/archive/html/qemu-devel/2006-03/msg00034.html Need to verify that it does not slow down x86 target. > 2. [PATCH][MIPS] add "lwu" instruction > http://lists.gnu.org/archive/html/qemu-devel/2006-04/msg00326.html On which MIPS CPU is it defined ? Need to track instruction sets exactly to be able to select a given MIPS CPU at compile time or dynamically. > 3. [PATCH] Add special MIPS multiply instructions > http://lists.gnu.org/archive/html/qemu-devel/2006-04/msg00375.html Same remark. > 4. [PATCH][MIPS] Enforce aligned pc > http://lists.gnu.org/archive/html/qemu-devel/2006-04/msg00484.html Can it happen on a real MIPS ? If not, an assert should be used for example. > 5.[PATCH 5-6/8] Mips improvements OK. Maybe expanding only the performance critical CP0 insn would have sufficed ? > http://lists.gnu.org/archive/html/qemu-devel/2006-05/msg00314.html > http://lists.gnu.org/archive/html/qemu-devel/2006-05/msg00315.html > > Note: Patch 7/8 was eaten by list. > > 6. [PATCH] Fix initial value for MIPS CP0 Config Register > http://lists.gnu.org/archive/html/qemu-devel/2006-05/msg00372.html Already done. > 7. [PATCH] Restructure MIPS r4k code > http://lists.gnu.org/archive/html/qemu-devel/2006-05/msg00429.html > Note: Pending until additional MIPS machines are added. Comment from > Fabrice: I prefer to wait until there is another mips machine (e.g. Malta). > Currently I see no reason to move the mips code as it is very small. > > 8. [PATCH] Add mips-user signal handling > http://lists.gnu.org/archive/html/qemu-devel/2006-06/msg00319.html OK. Need to check the handling of "env->PC += 4" in linux-user/main.c. I want to be sure there is not a better solution. Adding setup_rt_frame would be good too. > 9. [PATCH] Update MIPS status register with EXL and ERL bits at exception > http://lists.gnu.org/archive/html/qemu-devel/2006-06/msg00329.html OK but the following lines are suspicious: } else { env->CP0_ErrorEPC = env->PC; } - env->hflags = MIPS_HFLAG_ERL; + env->hflags |= MIPS_HFLAG_ERL; + env->CP0_Status &= (1 << CP0St_ERL); pc = 0xBFC00000; Fabrice.