From: Fabrice Bellard <fabrice@bellard.org>
To: mgroeger@sysgo.com
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] Re: MIPS instruction set configuration
Date: Tue, 27 Jun 2006 22:57:39 +0200 [thread overview]
Message-ID: <44A19BC3.1030607@bellard.org> (raw)
In-Reply-To: <Pine.LNX.4.63.0606271748590.12563@mag.sysgo.com>
Marius Groeger wrote:
> On Tue, 27 Jun 2006, Dirk Behme wrote:
>
>> Fabrice Bellard wrote:
>>
>>>>>> 3. [PATCH] Add special MIPS multiply instructions
>>>>>> http://lists.gnu.org/archive/html/qemu-devel/2006-04/msg00375.html
>>>>>
>>>>>
>>>>> Same remark.
>>>>
>>>>
>>>> These are NEC VR54xx specific extensions to the MIPS instruction set.
>>>>
>>>> They are used if you use GCC's -march=vr5400 option. See
>>>>
>>>> www.necelam.com/docs/files/1375_V2.pdf
>>>>
>>>> as well.
>>>
>>> Can you add some kind of define or dynamic processor definnition in
>>> your patch so that we can keep track of the exact instruction set ?
>>
>>
>> Yes, I will update the patch. Any ideas or proposals from anybody how
>> to do this the best way? Are there already examples from other
>> architectures?
>>
>> I think a define to be able to completely select/unselect it at
>> compile time combined with possibility for dynamic runtime selection
>> would be the best?
>
>
> I'm trying to make sense of a compile-time switch -- for the use to
> select you vr5400 based platform, I can't think of anything else than a
> new -M option (ie. a new machine definition). So the full set of
> possible insns must be present and be available depending on the machine
> (-M ...) at runtime.
>
> Or is it possible to compile qemu for a specific "-M machine"?
You should add a runtime selection system : see the ARM and PowerPC
targets (I would prefer a parameter to cpu_init(). It was not done that
way on PowerPC for legacy reasons). Each machine should be able to
select the processor it needs (and allow the user to change it if
needed, but it is not the main point). There is no good reason to make
the selection at compile time because the translator can efficiently
handle any CPU differences at runtime.
Regards,
Fabrice.
next prev parent reply other threads:[~2006-06-27 21:18 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-06-25 16:12 [Qemu-devel] Pending MIPS patches Dirk Behme
2006-06-25 16:39 ` Fabrice Bellard
2006-06-26 9:35 ` Marius Groeger
2006-06-26 15:35 ` Dirk Behme
2006-06-26 20:17 ` Fabrice Bellard
2006-06-27 15:45 ` MIPS instruction set configuration, was: " Dirk Behme
2006-06-27 15:55 ` [Qemu-devel] Re: MIPS instruction set configuration Marius Groeger
2006-06-27 20:57 ` Fabrice Bellard [this message]
2006-07-02 16:27 ` [Qemu-devel] [PATCH] " Dirk Behme
2006-07-02 23:16 ` Thiemo Seufer
2006-07-03 8:32 ` Fabrice Bellard
2006-07-03 9:50 ` Thiemo Seufer
2006-07-03 14:32 ` Dirk Behme
2006-07-03 14:53 ` Fabrice Bellard
2006-07-08 6:15 ` Dirk Behme
2006-07-03 14:20 ` Dirk Behme
2006-07-03 17:02 ` Thiemo Seufer
2006-07-03 18:41 ` Stefan Weil
2006-07-03 19:58 ` Thiemo Seufer
2006-07-08 6:19 ` Dirk Behme
2006-07-08 12:47 ` Thiemo Seufer
[not found] ` <44A001C7.8040303@gmail.com>
2006-06-26 17:27 ` [Qemu-devel] Pending MIPS patches Raphaël Rigo
2006-06-27 21:08 ` Fabrice Bellard
2006-06-27 21:15 ` Fabrice Bellard
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