From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1FvKwj-0005Sp-J9 for qemu-devel@nongnu.org; Tue, 27 Jun 2006 17:18:09 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1FvKwi-0005Rs-Oi for qemu-devel@nongnu.org; Tue, 27 Jun 2006 17:18:09 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1FvKwi-0005Rc-Ie for qemu-devel@nongnu.org; Tue, 27 Jun 2006 17:18:08 -0400 Received: from [84.96.92.61] (helo=sMtp.neuf.fr) by monty-python.gnu.org with esmtp (Exim 4.52) id 1FvL8t-0000Cd-Nz for qemu-devel@nongnu.org; Tue, 27 Jun 2006 17:30:43 -0400 Received: from [84.99.204.155] by sp604002mt.gpm.neuf.ld (Sun Java System Messaging Server 6.2-5.05 (built Feb 16 2006)) with ESMTP id <0J1J00G7NE8EWO30@sp604002mt.gpm.neuf.ld> for qemu-devel@nongnu.org; Tue, 27 Jun 2006 22:57:50 +0200 (CEST) Date: Tue, 27 Jun 2006 22:57:39 +0200 From: Fabrice Bellard Subject: Re: [Qemu-devel] Re: MIPS instruction set configuration In-reply-to: Message-id: <44A19BC3.1030607@bellard.org> MIME-version: 1.0 Content-type: text/plain; charset=us-ascii; format=flowed Content-transfer-encoding: 7BIT References: <449EB5FA.6070405@gmail.com> <449EBC39.3050701@bellard.org> <449FFEB2.1070305@gmail.com> <44A040DA.2050108@bellard.org> <44A1529D.1070306@gmail.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: mgroeger@sysgo.com Cc: qemu-devel@nongnu.org Marius Groeger wrote: > On Tue, 27 Jun 2006, Dirk Behme wrote: > >> Fabrice Bellard wrote: >> >>>>>> 3. [PATCH] Add special MIPS multiply instructions >>>>>> http://lists.gnu.org/archive/html/qemu-devel/2006-04/msg00375.html >>>>> >>>>> >>>>> Same remark. >>>> >>>> >>>> These are NEC VR54xx specific extensions to the MIPS instruction set. >>>> >>>> They are used if you use GCC's -march=vr5400 option. See >>>> >>>> www.necelam.com/docs/files/1375_V2.pdf >>>> >>>> as well. >>> >>> Can you add some kind of define or dynamic processor definnition in >>> your patch so that we can keep track of the exact instruction set ? >> >> >> Yes, I will update the patch. Any ideas or proposals from anybody how >> to do this the best way? Are there already examples from other >> architectures? >> >> I think a define to be able to completely select/unselect it at >> compile time combined with possibility for dynamic runtime selection >> would be the best? > > > I'm trying to make sense of a compile-time switch -- for the use to > select you vr5400 based platform, I can't think of anything else than a > new -M option (ie. a new machine definition). So the full set of > possible insns must be present and be available depending on the machine > (-M ...) at runtime. > > Or is it possible to compile qemu for a specific "-M machine"? You should add a runtime selection system : see the ARM and PowerPC targets (I would prefer a parameter to cpu_init(). It was not done that way on PowerPC for legacy reasons). Each machine should be able to select the processor it needs (and allow the user to change it if needed, but it is not the main point). There is no good reason to make the selection at compile time because the translator can efficiently handle any CPU differences at runtime. Regards, Fabrice.