From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1FxK0b-0006Kb-AD for qemu-devel@nongnu.org; Mon, 03 Jul 2006 04:42:21 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1FxK0a-0006KL-Et for qemu-devel@nongnu.org; Mon, 03 Jul 2006 04:42:20 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1FxK0a-0006KF-Be for qemu-devel@nongnu.org; Mon, 03 Jul 2006 04:42:20 -0400 Received: from [84.96.92.56] (helo=smTp.neuf.fr) by monty-python.gnu.org with esmtp (Exim 4.52) id 1FxKDz-00035g-RA for qemu-devel@nongnu.org; Mon, 03 Jul 2006 04:56:12 -0400 Received: from [84.102.211.65] by sp604003mt.gpm.neuf.ld (Sun Java System Messaging Server 6.2-5.05 (built Feb 16 2006)) with ESMTP id <0J1T00204JQ40U11@sp604003mt.gpm.neuf.ld> for qemu-devel@nongnu.org; Mon, 03 Jul 2006 10:32:29 +0200 (CEST) Date: Mon, 03 Jul 2006 10:32:21 +0200 From: Fabrice Bellard Subject: Re: [Qemu-devel] [PATCH] MIPS instruction set configuration In-reply-to: <20060702231636.GB18996@networkno.de> Message-id: <44A8D615.9060004@bellard.org> MIME-version: 1.0 Content-type: text/plain; charset=us-ascii; format=flowed Content-transfer-encoding: 7BIT References: <449EB5FA.6070405@gmail.com> <449EBC39.3050701@bellard.org> <449FFEB2.1070305@gmail.com> <44A040DA.2050108@bellard.org> <44A1529D.1070306@gmail.com> <44A19BC3.1030607@bellard.org> <44A7F3F1.5020909@gmail.com> <20060702231636.GB18996@networkno.de> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Thiemo Seufer wrote: > Dirk Behme wrote: > >>Fabrice Bellard wrote: >> >>>You should add a runtime selection system : see the ARM and PowerPC >>>targets (I would prefer a parameter to cpu_init(). It was not done that >>>way on PowerPC for legacy reasons). Each machine should be able to >>>select the processor it needs (and allow the user to change it if >>>needed, but it is not the main point). > > > It might be interesting for MIPS to decouple Machine and CPU somewhat. > E.g. the Malta board supports a number of different 32- and 64-bit CPUs. Each machine can add specific support for that (for example a -cpu option). It is likely to come at least for the PC machines. >>>There is no good reason to make >>>the selection at compile time because the translator can efficiently >>>handle any CPU differences at runtime. > > > I'm a bit dubious about this argument, each instruction needs to be > checked agains a tuple of values. How much performance loss would be > acceptable? It slows down the translator a bit, but most of the time is spent in the generated code, not in the translator (otherwise there is no point in doing dynamic translation !). >[...] > Unfortunately it is not that simple. We have the upward-compatible ISAs: >[...] I add suggest one more parameter to cpu_mips_set_model() to specify optional features. A function converting a CPU "string id" into an id + features would be interesting too. Fabrice.