From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1FxPTR-0003Lp-Co for qemu-devel@nongnu.org; Mon, 03 Jul 2006 10:32:29 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1FxPTO-0003LT-7F for qemu-devel@nongnu.org; Mon, 03 Jul 2006 10:32:28 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1FxPTN-0003LM-Vg for qemu-devel@nongnu.org; Mon, 03 Jul 2006 10:32:26 -0400 Received: from [64.233.182.190] (helo=nf-out-0910.google.com) by monty-python.gnu.org with esmtp (Exim 4.52) id 1FxPgq-0000kM-Sp for qemu-devel@nongnu.org; Mon, 03 Jul 2006 10:46:21 -0400 Received: by nf-out-0910.google.com with SMTP id o63so765649nfa for ; Mon, 03 Jul 2006 07:32:25 -0700 (PDT) Message-ID: <44A92A8A.8010200@gmail.com> Date: Mon, 03 Jul 2006 16:32:42 +0200 MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH] MIPS instruction set configuration References: <449EB5FA.6070405@gmail.com> <449EBC39.3050701@bellard.org> <449FFEB2.1070305@gmail.com> <44A040DA.2050108@bellard.org> <44A1529D.1070306@gmail.com> <44A19BC3.1030607@bellard.org> <44A7F3F1.5020909@gmail.com> <20060702231636.GB18996@networkno.de> <44A8D615.9060004@bellard.org> In-Reply-To: <44A8D615.9060004@bellard.org> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit From: Dirk Behme Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Fabrice Bellard wrote: > Each machine can add specific support for that (for example a -cpu > option). It is likely to come at least for the PC machines. ... > I add suggest one more parameter to cpu_mips_set_model() to specify > optional features. A function converting a CPU "string id" into an id + > features would be interesting too. Fabrice, do you will accept the patch if I remove the MIPS_FEATURE_ISAx options and convert MIPS_FEATURE_NEC_EXT to MIPS_FEATURE_NEC_VR5400 as described in my previous mail? I consider this patch as a *first* step from hardcoded and compile time selected MIPS machine to flexible configuration as proposed by you and Thiemo. Other patches, for example with (really nice!) features above, can follow then and take this first patch as basis. With this, several small patches will improve MIPS step by step. I'd like to avoid a 'perfect, but unreadable, big & never ready' patch. And, with several small patches, more people can contribute ;) Many thanks for the comments Dirk