Re: [Qemu-devel] [PATCH] MIPS instruction set configuration

[Stefan Weil <weil@mail.berlios.de>]

Hi all,

just for information about current projects for QEMU MIPS:

my machine is AR7 which includes a MIPS 4KEc core.
This core supports the MIPS32R2 architecture and has no FPU.

As far as I know the MIPS architecture, most CPU features
can be read from well defined bits and bytes in the CP0 registers.

These registers should be set by every machine definition in QEMU.

So the emulation (translator) code could get all information needed from
the CP0 registers which are part of variable "env". There is no
need to introduce new defines or variables to get endianess,
instruction set, presence of FPU or internal timer, and other
features. And if generic property bits are not enough:
the processor identification is part of the CP0 registers, too.

Of course, one might mirror some features in extra variables for
performance reasons.

What do you think of my proposal?

Regards
Stefan

>
>Well, there is no CPU named "R4Kc". What qemu emulates today resembles
>mostly a 4kc, that is a MIPS32R1 CPU which has no FPU support.
>
>I figure you are going for emulation of a vr5400, a MIPS-IV CPU with
>FPU and some additional multiply-add instructions.
>
>What I hope to get done is support for MIPS32R2 including FPU, this is
>close to a 24kf.
>
>
>Thiemo
>
>