From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1FxTMG-0002Rk-PC for qemu-devel@nongnu.org; Mon, 03 Jul 2006 14:41:20 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1FxTMF-0002RP-MZ for qemu-devel@nongnu.org; Mon, 03 Jul 2006 14:41:20 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1FxTMF-0002RF-FD for qemu-devel@nongnu.org; Mon, 03 Jul 2006 14:41:19 -0400 Received: from [212.227.126.188] (helo=moutng.kundenserver.de) by monty-python.gnu.org with esmtp (Exim 4.52) id 1FxTZk-0002Mq-Gh for qemu-devel@nongnu.org; Mon, 03 Jul 2006 14:55:16 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) by flubber.weilnetz.de (Postfix) with ESMTP id 111DEF2C46 for ; Mon, 3 Jul 2006 20:41:06 +0200 (CEST) Message-ID: <44A964C1.307@mail.berlios.de> Date: Mon, 03 Jul 2006 20:41:05 +0200 From: Stefan Weil MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH] MIPS instruction set configuration References: <449EB5FA.6070405@gmail.com> <449EBC39.3050701@bellard.org> <449FFEB2.1070305@gmail.com> <44A040DA.2050108@bellard.org> <44A1529D.1070306@gmail.com> <44A19BC3.1030607@bellard.org> <44A7F3F1.5020909@gmail.com> <20060702231636.GB18996@networkno.de> <44A927BD.4010206@gmail.com> <20060703170235.GB6625@networkno.de> In-Reply-To: <20060703170235.GB6625@networkno.de> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Hi all, just for information about current projects for QEMU MIPS: my machine is AR7 which includes a MIPS 4KEc core. This core supports the MIPS32R2 architecture and has no FPU. As far as I know the MIPS architecture, most CPU features can be read from well defined bits and bytes in the CP0 registers. These registers should be set by every machine definition in QEMU. So the emulation (translator) code could get all information needed from the CP0 registers which are part of variable "env". There is no need to introduce new defines or variables to get endianess, instruction set, presence of FPU or internal timer, and other features. And if generic property bits are not enough: the processor identification is part of the CP0 registers, too. Of course, one might mirror some features in extra variables for performance reasons. What do you think of my proposal? Regards Stefan > >Well, there is no CPU named "R4Kc". What qemu emulates today resembles >mostly a 4kc, that is a MIPS32R1 CPU which has no FPU support. > >I figure you are going for emulation of a vr5400, a MIPS-IV CPU with >FPU and some additional multiply-add instructions. > >What I hope to get done is support for MIPS32R2 including FPU, this is >close to a 24kf. > > >Thiemo > >