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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id d5-20020a17090acd0500b001b9c05b075dsm12967803pju.44.2022.04.08.16.39.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 Apr 2022 16:39:37 -0700 (PDT) Message-ID: <44ba8f25-1e3e-b41e-c83a-1f2c20655232@linaro.org> Date: Fri, 8 Apr 2022 16:39:35 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 05/41] target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2 Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20220408141550.1271295-1-peter.maydell@linaro.org> <20220408141550.1271295-6-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20220408141550.1271295-6-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 4/8/22 07:15, Peter Maydell wrote: > In a GICv3, it is impossible for the GIC to deliver a VIRQ or VFIQ to > the CPU unless the CPU has EL2, because VIRQ and VFIQ are only > configurable via EL2-only system registers. Moreover, in our > implementation we were only calculating and updating the state of the > VIRQ and VFIQ lines in gicv3_cpuif_virt_irq_fiq_update() when those > EL2 system registers changed. We were therefore able to assert in > arm_cpu_set_irq() that we didn't see a VIRQ or VFIQ line update if > EL2 wasn't present. > > This assumption no longer holds with GICv4: > * even if the CPU does not have EL2 the guest is able to cause the > GIC to deliver a virtual LPI by programming the ITS (which is a > silly thing for it to do, but possible) > * because we now need to recalculate the state of the VIRQ and VFIQ > lines in more cases than just "some EL2 GIC sysreg was written", > we will see calls to arm_cpu_set_irq() for "VIRQ is 0, VFIQ is 0" > even if the guest is not using the virtual LPI parts of the ITS > > Remove the assertions, and instead simply ignore the state of the > VIRQ and VFIQ lines if the CPU does not have EL2. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.c | 12 ++++++++++-- > 1 file changed, 10 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson r~