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From: Paolo Bonzini <pbonzini@redhat.com>
To: Thomas Huth <thuth@redhat.com>, qemu-devel@nongnu.org
Cc: kraxel@redhat.com, mst@redhat.com
Subject: Re: [PATCH] libqos: usb-hcd-ehci: use 32-bit write for config register
Date: Wed, 24 Jun 2020 10:01:58 +0200	[thread overview]
Message-ID: <44bd9295-411d-6f72-923c-c15c67653ed4@redhat.com> (raw)
In-Reply-To: <9d1c30ab-9944-712a-16e7-c2d3240f23e1@redhat.com>

On 24/06/20 09:47, Thomas Huth wrote:
>>
>>   {
>>       /* hands over all ports from companion uhci to ehci */
>> -    qpci_io_writew(ehci1.dev, ehci1.bar, 0x60, 1);
>> +    qpci_io_writel(ehci1.dev, ehci1.bar, 0x60, 1);
>>   }
>>     static void pci_uhci_port_2(void)
> 
> Passes "make check-qtest-x86_64" on a s390x host, too:
> 
> Tested-by: Thomas Huth <thuth@redhat.com>

Ah, I see what you mean now, so I'll clarify.  Endianness is handled by
the memory core and libqos so for little-endian devices (such as PCI
devices) it's okay.  For big-endian using the wrong size would not work,
but it should fail the same on LE and BE hosts.  endianness-test checks
that.

Paolo



      reply	other threads:[~2020-06-24  8:03 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-23 16:18 [PATCH] libqos: usb-hcd-ehci: use 32-bit write for config register Paolo Bonzini
2020-06-23 20:56 ` Michael S. Tsirkin
2020-06-24  5:59   ` Paolo Bonzini
2020-06-24  7:47 ` Thomas Huth
2020-06-24  8:01   ` Paolo Bonzini [this message]

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