* [PATCH] target/riscv: Set vtype.vill on CPU reset
@ 2024-09-30 16:52 Rob Bradford
2024-10-02 13:15 ` Daniel Henrique Barboza
2024-10-08 1:30 ` Alistair Francis
0 siblings, 2 replies; 3+ messages in thread
From: Rob Bradford @ 2024-09-30 16:52 UTC (permalink / raw)
To: qemu-devel
Cc: Rob Bradford, Palmer Dabbelt, Alistair Francis, Bin Meng,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
open list:RISC-V TCG CPUs
The RISC-V unprivileged specification "31.3.11. State of Vector
Extension at Reset" has a note that recommends vtype.vill be set on
reset as part of ensuring that the vector extension have a consistent
state at reset.
This change now makes QEMU consistent with Spike which sets vtype.vill
on reset.
Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4bda754b01..af602e3caf 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -997,6 +997,7 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
cs->exception_index = RISCV_EXCP_NONE;
env->load_res = -1;
set_default_nan_mode(1, &env->fp_status);
+ env->vill = true;
#ifndef CONFIG_USER_ONLY
if (cpu->cfg.debug) {
--
2.46.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] target/riscv: Set vtype.vill on CPU reset
2024-09-30 16:52 [PATCH] target/riscv: Set vtype.vill on CPU reset Rob Bradford
@ 2024-10-02 13:15 ` Daniel Henrique Barboza
2024-10-08 1:30 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Daniel Henrique Barboza @ 2024-10-02 13:15 UTC (permalink / raw)
To: Rob Bradford, qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei,
open list:RISC-V TCG CPUs
On 9/30/24 1:52 PM, Rob Bradford wrote:
> The RISC-V unprivileged specification "31.3.11. State of Vector
> Extension at Reset" has a note that recommends vtype.vill be set on
> reset as part of ensuring that the vector extension have a consistent
> state at reset.
>
> This change now makes QEMU consistent with Spike which sets vtype.vill
> on reset.
>
> Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 4bda754b01..af602e3caf 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -997,6 +997,7 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
> cs->exception_index = RISCV_EXCP_NONE;
> env->load_res = -1;
> set_default_nan_mode(1, &env->fp_status);
> + env->vill = true;
>
> #ifndef CONFIG_USER_ONLY
> if (cpu->cfg.debug) {
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] target/riscv: Set vtype.vill on CPU reset
2024-09-30 16:52 [PATCH] target/riscv: Set vtype.vill on CPU reset Rob Bradford
2024-10-02 13:15 ` Daniel Henrique Barboza
@ 2024-10-08 1:30 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2024-10-08 1:30 UTC (permalink / raw)
To: Rob Bradford
Cc: qemu-devel, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs
On Tue, Oct 1, 2024 at 2:53 AM Rob Bradford <rbradford@rivosinc.com> wrote:
>
> The RISC-V unprivileged specification "31.3.11. State of Vector
> Extension at Reset" has a note that recommends vtype.vill be set on
> reset as part of ensuring that the vector extension have a consistent
> state at reset.
>
> This change now makes QEMU consistent with Spike which sets vtype.vill
> on reset.
>
> Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 4bda754b01..af602e3caf 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -997,6 +997,7 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
> cs->exception_index = RISCV_EXCP_NONE;
> env->load_res = -1;
> set_default_nan_mode(1, &env->fp_status);
> + env->vill = true;
>
> #ifndef CONFIG_USER_ONLY
> if (cpu->cfg.debug) {
> --
> 2.46.0
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2024-10-08 1:31 UTC | newest]
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2024-10-02 13:15 ` Daniel Henrique Barboza
2024-10-08 1:30 ` Alistair Francis
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