From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: richard.henderson@linaro.org, wxy194768@alibaba-inc.com,
wenmeng_zhang@c-sky.com,
Alistair Francis <alistair.francis@wdc.com>,
palmer@dabbelt.com, Laurent Vivier <laurent@vivier.eu>
Subject: Re: [PATCH v12 08/61] target/riscv: add fault-only-first unit stride load
Date: Sat, 17 Dec 2022 19:21:53 +0100 [thread overview]
Message-ID: <44ff8209-236d-cd2f-25cd-d608303ad96f@linaro.org> (raw)
In-Reply-To: <20200701152549.1218-9-zhiwei_liu@c-sky.com>
(unburying an old patch)
On 1/7/20 17:24, LIU Zhiwei wrote:
> The unit-stride fault-only-fault load instructions are used to
> vectorize loops with data-dependent exit conditions(while loops).
> These instructions execute as a regular load except that they
> will only take a trap on element 0.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/riscv/helper.h | 22 +++++
> target/riscv/insn32.decode | 7 ++
> target/riscv/insn_trans/trans_rvv.inc.c | 73 ++++++++++++++++
> target/riscv/vector_helper.c | 110 ++++++++++++++++++++++++
> 4 files changed, 212 insertions(+)
> +/*
> + *** unit-stride fault-only-fisrt load instructions
> + */
> +static inline void
> +vext_ldff(void *vd, void *v0, target_ulong base,
> + CPURISCVState *env, uint32_t desc,
> + vext_ldst_elem_fn *ldst_elem,
> + clear_fn *clear_elem,
> + uint32_t esz, uint32_t msz, uintptr_t ra)
> +{
> + void *host;
> + uint32_t i, k, vl = 0;
> + uint32_t mlen = vext_mlen(desc);
> + uint32_t nf = vext_nf(desc);
> + uint32_t vm = vext_vm(desc);
> + uint32_t vlmax = vext_maxsz(desc) / esz;
> + target_ulong addr, offset, remain;
> +
> + /* probe every access*/
> + for (i = 0; i < env->vl; i++) {
> + if (!vm && !vext_elem_mask(v0, mlen, i)) {
> + continue;
> + }
> + addr = base + nf * i * msz;
> + if (i == 0) {
> + probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
Shouldn't we check page_check_range() in user-mode here?
> + } else {
> + /* if it triggers an exception, no need to check watchpoint */
> + remain = nf * msz;
> + while (remain > 0) {
> + offset = -(addr | TARGET_PAGE_MASK);
> + host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD,
> + cpu_mmu_index(env, false));
> + if (host) {
> +#ifdef CONFIG_USER_ONLY
> + if (page_check_range(addr, nf * msz, PAGE_READ) < 0) {
> + vl = i;
> + goto ProbeSuccess;
> + }
> +#else
> + probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
> +#endif
> + } else {
> + vl = i;
> + goto ProbeSuccess;
> + }
> + if (remain <= offset) {
> + break;
> + }
> + remain -= offset;
> + addr += offset;
> + }
> + }
> + }
> +ProbeSuccess:
> + /* load bytes from guest memory */
> + if (vl != 0) {
> + env->vl = vl;
> + }
> + for (i = 0; i < env->vl; i++) {
> + k = 0;
> + if (!vm && !vext_elem_mask(v0, mlen, i)) {
> + continue;
> + }
> + while (k < nf) {
> + target_ulong addr = base + (i * nf + k) * msz;
> + ldst_elem(env, addr, i + k * vlmax, vd, ra);
> + k++;
> + }
> + }
> + /* clear tail elements */
> + if (vl != 0) {
> + return;
> + }
> + for (k = 0; k < nf; k++) {
> + clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
> + }
> +}
next prev parent reply other threads:[~2022-12-17 18:22 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-01 15:24 [PATCH v12 00/61] target/riscv: support vector extension v0.7.1 LIU Zhiwei
2020-07-01 15:24 ` [PATCH v12 01/61] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-07-01 15:24 ` [PATCH v12 02/61] target/riscv: implementation-defined constant parameters LIU Zhiwei
2020-07-01 15:24 ` [PATCH v12 03/61] target/riscv: support vector extension csr LIU Zhiwei
2020-07-01 15:24 ` [PATCH v12 04/61] target/riscv: add vector configure instruction LIU Zhiwei
2020-07-01 15:24 ` [PATCH v12 05/61] target/riscv: add an internals.h header LIU Zhiwei
2020-07-01 15:24 ` [PATCH v12 06/61] target/riscv: add vector stride load and store instructions LIU Zhiwei
2020-07-01 15:24 ` [PATCH v12 07/61] target/riscv: add vector index " LIU Zhiwei
2020-07-01 15:24 ` [PATCH v12 08/61] target/riscv: add fault-only-first unit stride load LIU Zhiwei
2022-12-17 18:21 ` Philippe Mathieu-Daudé [this message]
2022-12-17 18:28 ` Richard Henderson
2020-07-01 15:24 ` [PATCH v12 09/61] target/riscv: add vector amo operations LIU Zhiwei
2020-07-01 15:24 ` [PATCH v12 10/61] target/riscv: vector single-width integer add and subtract LIU Zhiwei
2020-07-01 15:24 ` [PATCH v12 11/61] target/riscv: vector widening " LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 13/61] target/riscv: vector bitwise logical instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 14/61] target/riscv: vector single-width bit shift instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 15/61] target/riscv: vector narrowing integer right " LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 16/61] target/riscv: vector integer comparison instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 17/61] target/riscv: vector integer min/max instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 18/61] target/riscv: vector single-width integer multiply instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 19/61] target/riscv: vector integer divide instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 20/61] target/riscv: vector widening integer multiply instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 21/61] target/riscv: vector single-width integer multiply-add instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 22/61] target/riscv: vector widening " LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 23/61] target/riscv: vector integer merge and move instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 24/61] target/riscv: vector single-width saturating add and subtract LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 25/61] target/riscv: vector single-width averaging " LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 27/61] target/riscv: vector widening saturating scaled multiply-add LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 28/61] target/riscv: vector single-width scaling shift instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 29/61] target/riscv: vector narrowing fixed-point clip instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 30/61] target/riscv: vector single-width floating-point add/subtract instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 31/61] target/riscv: vector widening " LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 32/61] target/riscv: vector single-width floating-point multiply/divide instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 33/61] target/riscv: vector widening floating-point multiply LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 35/61] target/riscv: vector widening " LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 36/61] target/riscv: vector floating-point square-root instruction LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 37/61] target/riscv: vector floating-point min/max instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 38/61] target/riscv: vector floating-point sign-injection instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 39/61] target/riscv: vector floating-point compare instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 40/61] target/riscv: vector floating-point classify instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 41/61] target/riscv: vector floating-point merge instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 42/61] target/riscv: vector floating-point/integer type-convert instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 43/61] target/riscv: widening " LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 44/61] target/riscv: narrowing " LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 45/61] target/riscv: vector single-width integer reduction instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 46/61] target/riscv: vector wideing " LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 47/61] target/riscv: vector single-width floating-point " LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 48/61] target/riscv: vector widening " LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 49/61] target/riscv: vector mask-register logical instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 50/61] target/riscv: vector mask population count vmpopc LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 51/61] target/riscv: vmfirst find-first-set mask bit LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 52/61] target/riscv: set-X-first " LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 53/61] target/riscv: vector iota instruction LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 54/61] target/riscv: vector element index instruction LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 55/61] target/riscv: integer extract instruction LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 56/61] target/riscv: integer scalar move instruction LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 57/61] target/riscv: floating-point scalar move instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 58/61] target/riscv: vector slide instructions LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 59/61] target/riscv: vector register gather instruction LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 60/61] target/riscv: vector compress instruction LIU Zhiwei
2020-07-01 15:25 ` [PATCH v12 61/61] target/riscv: configure and turn on vector extension from command line LIU Zhiwei
2020-07-01 19:38 ` [PATCH v12 00/61] target/riscv: support vector extension v0.7.1 no-reply
2020-07-02 3:32 ` Alistair Francis
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