From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1GPmZP-0002J1-Iu for qemu-devel@nongnu.org; Tue, 19 Sep 2006 16:51:55 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1GPmZM-00028f-Ex for qemu-devel@nongnu.org; Tue, 19 Sep 2006 16:51:55 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1GPmZM-00027B-0J for qemu-devel@nongnu.org; Tue, 19 Sep 2006 16:51:52 -0400 Received: from [147.11.1.11] (helo=mail.wrs.com) by monty-python.gnu.org with esmtp (Exim 4.52) id 1GPmcU-0004QJ-Ea for qemu-devel@nongnu.org; Tue, 19 Sep 2006 16:55:06 -0400 Received: from ala-mail04.corp.ad.wrs.com (ala-mail04 [147.11.57.145]) by mail.wrs.com (8.13.6/8.13.3) with ESMTP id k8JKpn5o017869 for ; Tue, 19 Sep 2006 13:51:49 -0700 (PDT) Message-ID: <45105864.9090902@windriver.com> Date: Tue, 19 Sep 2006 15:51:48 -0500 From: Jason Wessel MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------000005040707040902070108" Subject: [Qemu-devel] [PATCH] x86_64 debug registers for gdb Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. --------------000005040707040902070108 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit This patch fixes the registers for the 'g' and 'G' packets for the qemu-system-x86_64 target. It allows gdb 6.5 to debug a linux kernel and get a stack back trace. signed-off-by: jason.wessel@windriver.com Thanks, Jason. --------------000005040707040902070108 Content-Type: text/plain; name="x86-64_gdb.patch" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="x86-64_gdb.patch" Index: qemu/gdbstub.c =================================================================== --- qemu.orig/gdbstub.c +++ qemu/gdbstub.c @@ -184,9 +184,70 @@ static int put_packet(GDBState *s, char } return 0; } +#if defined(TARGET_X86_64) +/* Defines from GDB register struct numbers */ +#define _RAX 0 +#define _RDX 1 +#define _RCX 2 +#define _RBX 3 +#define _RSI 4 +#define _RDI 5 +#define _RBP 6 +#define _RSP 7 +#define _R8 8 +#define _R9 9 +#define _R10 10 +#define _R11 11 +#define _R12 12 +#define _R13 13 +#define _R14 14 +#define _R15 15 +#define _PC 16 +#define _PS 17 -#if defined(TARGET_I386) +static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) +{ + uint64_t *registers = (uint64_t *)mem_buf; + int i; + + registers[_RAX] = env->regs[R_EAX]; + registers[_RBX] = env->regs[R_EBX]; + registers[_RCX] = env->regs[R_ECX]; + registers[_RDX] = env->regs[R_EDX]; + registers[_RSI] = env->regs[R_ESI]; + registers[_RDI] = env->regs[R_EDI]; + registers[_RBP] = env->regs[R_EBP]; + registers[_RSP] = env->regs[R_ESP]; + for (i = 8; i < 16; i++) + registers[i] = env->regs[i]; + registers[_PC] = env->eip; + registers[_PS] = env->eflags; + for(i = 0; i < 18; i++) + tswapl(registers[i]); + + return 18 * 8; +} + +static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size) +{ + uint32_t *registers = (uint32_t *)mem_buf; + int i; + + env->regs[R_EAX] = tswapl(registers[_RAX]); + env->regs[R_EBX] = tswapl(registers[_RBX]); + env->regs[R_ECX] = tswapl(registers[_RCX]); + env->regs[R_EDX] = tswapl(registers[_RDX]); + env->regs[R_ESI] = tswapl(registers[_RSI]); + env->regs[R_EDI] = tswapl(registers[_RDI]); + env->regs[R_EBP] = tswapl(registers[_RBP]); + env->regs[R_ESP] = tswapl(registers[_RSP]); + for (i = 8; i < 16; i++) + env->regs[i] = tswapl(registers[i]); + env->eip = tswapl(registers[_PC]); + env->eflags = tswapl(registers[_PS]); +} +#elif defined(TARGET_I386) static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) { uint32_t *registers = (uint32_t *)mem_buf; --------------000005040707040902070108--