[Qemu-devel] proprietary MIPS based ASIC

[Qemu-devel] proprietary MIPS based ASIC

[larytet.39605663]

 Hello,



I am a software developer working in a chip maker. One of our chips
- dual MIPS 4Kec with GPON/BPON related peripherals, DDR, interrupt contorller,
SPI, I2C and UART. This is SoC (System ooon Chip) which should run small chunk
of software, like proprietary protocol stack, small RTOS (may be commercial
one like Velosity or OSS like eCOS)



How hard it is going to be to emulate
full system like this ? Any examples/tutorials where to start ? Any experience
of porting QEMU to other platforms ? Let's say MIPS+DDR+simple interrupt controller
and no other peripherals 

Re: [Qemu-devel] proprietary MIPS based ASIC

[Paul Brook]

On Thursday 26 October 2006 08:50, larytet.39605663@bloglines.com wrote:
>  Hello,
>
>
>
> I am a software developer working in a chip maker. One of our chips
> - dual MIPS 4Kec with GPON/BPON related peripherals, DDR, interrupt
> contorller, SPI, I2C and UART. This is SoC (System ooon Chip) which should
> run small chunk of software, like proprietary protocol stack, small RTOS
> (may be commercial one like Velosity or OSS like eCOS)
>
>
>
> How hard it is going to be to emulate
> full system like this ? Any examples/tutorials where to start ? Any
> experience of porting QEMU to other platforms ? Let's say MIPS+DDR+simple
> interrupt controller and no other peripherals

I suggest you look at the existing targets. e.g. the existing mips and ARM 
targets. IMHO it's not that hard to add new boards.

Paul

Re: [Qemu-devel] proprietary MIPS based ASIC

[Rob Landley]

On Thursday 26 October 2006 8:31 am, Paul Brook wrote:
> > How hard it is going to be to emulate
> > full system like this ? Any examples/tutorials where to start ? Any
> > experience of porting QEMU to other platforms ? Let's say MIPS+DDR+simple
> > interrupt controller and no other peripherals
> 
> I suggest you look at the existing targets. e.g. the existing mips and ARM 
> targets. IMHO it's not that hard to add new boards.

The tech docs at http://www.qemu.org/user-doc.html could really use some more 
information on this area.

The "hw" directory contains both definitions of individual pieces of hardware 
(such as i8259.or ide.c) and motherboards that integrate lots of pieces of 
hardware together (pc.c or integratorcp.c).  They're treated as 
interchangeable, both of them are initialized with a function ending 
in "_init", and there's no easy way to distinguish between them except by 
inspection.  (I could easily be wrong about this, but if so I haven't found 
the pattern or documentation yet.)

Rob
-- 
"Perfection is reached, not when there is no longer anything to add, but
when there is no longer anything to take away." - Antoine de Saint-Exupery

Re: [Qemu-devel] proprietary MIPS based ASIC

[Stefan Weil]

There exists a QEMU system emulation for AR7 based DSL routers.

AR7 is a SoC based on MIPS 4KEc, so some part of the
work needed for your system was done there.

See http://ar7-firmware.berlios.de/ for more information.
Patched QEMU sources are in Subversion on BerliOS.

Regards
Stefan

larytet.39605663@bloglines.com schrieb:
> Hello,
>
>
>
> I am a software developer working in a chip maker. One of our chips
> - dual MIPS 4Kec with GPON/BPON related peripherals, DDR, interrupt
> contorller,
> SPI, I2C and UART. This is SoC (System ooon Chip) which should run
> small chunk
> of software, like proprietary protocol stack, small RTOS (may be
> commercial
> one like Velosity or OSS like eCOS)
>