* [PATCH v2 0/4] target/ppc: Fix VSX instructions register access
@ 2021-12-13 12:09 Victor Colombo
2021-12-13 12:09 ` [PATCH v2 1/4] target/ppc: Fix xs{max, min}[cj]dp to use VSX registers Victor Colombo
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Victor Colombo @ 2021-12-13 12:09 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: danielhb413, richard.henderson, groug, victor.colombo, clg,
matheus.ferst, david
Instructions xscvqpdp, xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are
using the wrong registers, which yields the wrong result when using
them.
This patch series fixes this issue by correcting the registers used.
It also takes the opportunity to move these instructions to decodetree.
v2:
- Change ISA310 flag to ISA300 in xscvqpdp
Matheus Ferst (2):
target/ppc: fix xscvqpdp register access
target/ppc: move xscvqpdp to decodetree
Victor Colombo (2):
target/ppc: Fix xs{max,min}[cj]dp to use VSX registers
target/ppc: Move xs{max,min}[cj]dp to decodetree
target/ppc/fpu_helper.c | 14 +++-----
target/ppc/helper.h | 10 +++---
target/ppc/insn32.decode | 21 +++++++++--
target/ppc/translate/vsx-impl.c.inc | 55 +++++++++++++++++++++--------
target/ppc/translate/vsx-ops.c.inc | 5 ---
5 files changed, 68 insertions(+), 37 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/4] target/ppc: Fix xs{max, min}[cj]dp to use VSX registers
2021-12-13 12:09 [PATCH v2 0/4] target/ppc: Fix VSX instructions register access Victor Colombo
@ 2021-12-13 12:09 ` Victor Colombo
2021-12-13 12:09 ` [PATCH v2 2/4] target/ppc: Move xs{max,min}[cj]dp to decodetree Victor Colombo
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Victor Colombo @ 2021-12-13 12:09 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: danielhb413, richard.henderson, groug, victor.colombo, clg,
matheus.ferst, david
PPC instruction xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are using
vector registers when they should be using VSX ones. This happens
because the instructions are using GEN_VSX_HELPER_R3, which adds 32
to the register numbers, effectively making them vector registers.
This patch fixes it by changing these instructions to use
GEN_VSX_HELPER_X3.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Victor Colombo <victor.colombo@eldorado.org.br>
---
target/ppc/fpu_helper.c | 4 ++--
target/ppc/helper.h | 8 ++++----
target/ppc/translate/vsx-impl.c.inc | 8 ++++----
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index c4896cecc8..ad41ef1606 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2420,7 +2420,7 @@ VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i))
VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i))
#define VSX_MAX_MINC(name, max) \
-void helper_##name(CPUPPCState *env, uint32_t opcode, \
+void helper_##name(CPUPPCState *env, \
ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
{ \
ppc_vsr_t t = *xt; \
@@ -2455,7 +2455,7 @@ VSX_MAX_MINC(xsmaxcdp, 1);
VSX_MAX_MINC(xsmincdp, 0);
#define VSX_MAX_MINJ(name, max) \
-void helper_##name(CPUPPCState *env, uint32_t opcode, \
+void helper_##name(CPUPPCState *env, \
ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
{ \
ppc_vsr_t t = *xt; \
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 627811cefc..12a3d5f269 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -392,10 +392,10 @@ DEF_HELPER_4(xscmpoqp, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscmpuqp, void, env, i32, vsr, vsr)
DEF_HELPER_4(xsmaxdp, void, env, vsr, vsr, vsr)
DEF_HELPER_4(xsmindp, void, env, vsr, vsr, vsr)
-DEF_HELPER_5(xsmaxcdp, void, env, i32, vsr, vsr, vsr)
-DEF_HELPER_5(xsmincdp, void, env, i32, vsr, vsr, vsr)
-DEF_HELPER_5(xsmaxjdp, void, env, i32, vsr, vsr, vsr)
-DEF_HELPER_5(xsminjdp, void, env, i32, vsr, vsr, vsr)
+DEF_HELPER_4(xsmaxcdp, void, env, vsr, vsr, vsr)
+DEF_HELPER_4(xsmincdp, void, env, vsr, vsr, vsr)
+DEF_HELPER_4(xsmaxjdp, void, env, vsr, vsr, vsr)
+DEF_HELPER_4(xsminjdp, void, env, vsr, vsr, vsr)
DEF_HELPER_3(xscvdphp, void, env, vsr, vsr)
DEF_HELPER_4(xscvdpqp, void, env, i32, vsr, vsr)
DEF_HELPER_3(xscvdpsp, void, env, vsr, vsr)
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index c0e38060b4..02df75339e 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1098,10 +1098,10 @@ GEN_VSX_HELPER_R2_AB(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_X3(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
-GEN_VSX_HELPER_R3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300)
-GEN_VSX_HELPER_R3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300)
-GEN_VSX_HELPER_R3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300)
-GEN_VSX_HELPER_R3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300)
+GEN_VSX_HELPER_X3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300)
+GEN_VSX_HELPER_X3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300)
+GEN_VSX_HELPER_X3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300)
+GEN_VSX_HELPER_X3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300)
GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/4] target/ppc: Move xs{max,min}[cj]dp to decodetree
2021-12-13 12:09 [PATCH v2 0/4] target/ppc: Fix VSX instructions register access Victor Colombo
2021-12-13 12:09 ` [PATCH v2 1/4] target/ppc: Fix xs{max, min}[cj]dp to use VSX registers Victor Colombo
@ 2021-12-13 12:09 ` Victor Colombo
2021-12-13 12:09 ` [PATCH v2 3/4] target/ppc: fix xscvqpdp register access Victor Colombo
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Victor Colombo @ 2021-12-13 12:09 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: danielhb413, richard.henderson, groug, victor.colombo, clg,
matheus.ferst, david
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Victor Colombo <victor.colombo@eldorado.org.br>
---
target/ppc/insn32.decode | 17 +++++++++++++---
target/ppc/translate/vsx-impl.c.inc | 30 +++++++++++++++++++++++++----
target/ppc/translate/vsx-ops.c.inc | 4 ----
3 files changed, 40 insertions(+), 11 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index e135b8aba4..759b2a9aa5 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -123,10 +123,14 @@
&X_vrt_frbp vrt frbp
@X_vrt_frbp ...... vrt:5 ..... ....0 .......... . &X_vrt_frbp frbp=%x_frbp
+%xx_xt 0:1 21:5
+%xx_xb 1:1 11:5
+%xx_xa 2:1 16:5
&XX2 xt xb uim:uint8_t
-%xx2_xt 0:1 21:5
-%xx2_xb 1:1 11:5
-@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx2_xt xb=%xx2_xb
+@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx_xt xb=%xx_xb
+
+&XX3 xt xa xb
+@XX3 ...... ..... ..... ..... ........ ... &XX3 xt=%xx_xt xa=%xx_xa xb=%xx_xb
&Z22_bf_fra bf fra dm
@Z22_bf_fra ...... bf:3 .. fra:5 dm:6 ......... . &Z22_bf_fra
@@ -427,3 +431,10 @@ XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2
## VSX Vector Load Special Value Instruction
LXVKQ 111100 ..... 11111 ..... 0101101000 . @X_uim5
+
+## VSX Comparison Instructions
+
+XSMAXCDP 111100 ..... ..... ..... 10000000 ... @XX3
+XSMINCDP 111100 ..... ..... ..... 10001000 ... @XX3
+XSMAXJDP 111100 ..... ..... ..... 10010000 ... @XX3
+XSMINJDP 111100 ..... ..... ..... 10011000 ... @XX3
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 02df75339e..e2447750dd 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1098,10 +1098,6 @@ GEN_VSX_HELPER_R2_AB(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_R2_AB(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_X3(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_X3(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
-GEN_VSX_HELPER_X3(xsmaxcdp, 0x00, 0x10, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X3(xsmincdp, 0x00, 0x11, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X3(xsmaxjdp, 0x00, 0x12, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X3(xsminjdp, 0x00, 0x12, 0, PPC2_ISA300)
GEN_VSX_HELPER_X2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
GEN_VSX_HELPER_X2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
GEN_VSX_HELPER_R2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
@@ -2185,6 +2181,32 @@ TRANS(XXBLENDVH, do_xxblendv, MO_16)
TRANS(XXBLENDVW, do_xxblendv, MO_32)
TRANS(XXBLENDVD, do_xxblendv, MO_64)
+static bool do_xsmaxmincjdp(DisasContext *ctx, arg_XX3 *a,
+ void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr))
+{
+ TCGv_ptr xt, xa, xb;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_VSX(ctx);
+
+ xt = gen_vsr_ptr(a->xt);
+ xa = gen_vsr_ptr(a->xa);
+ xb = gen_vsr_ptr(a->xb);
+
+ helper(cpu_env, xt, xa, xb);
+
+ tcg_temp_free_ptr(xt);
+ tcg_temp_free_ptr(xa);
+ tcg_temp_free_ptr(xb);
+
+ return true;
+}
+
+TRANS(XSMAXCDP, do_xsmaxmincjdp, gen_helper_xsmaxcdp)
+TRANS(XSMINCDP, do_xsmaxmincjdp, gen_helper_xsmincdp)
+TRANS(XSMAXJDP, do_xsmaxmincjdp, gen_helper_xsmaxjdp)
+TRANS(XSMINJDP, do_xsmaxmincjdp, gen_helper_xsminjdp)
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index 152d1e5c3b..f980bc1bae 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -207,10 +207,6 @@ GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001),
GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001),
GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
-GEN_XX3FORM(xsmaxcdp, 0x00, 0x10, PPC2_ISA300),
-GEN_XX3FORM(xsmincdp, 0x00, 0x11, PPC2_ISA300),
-GEN_XX3FORM(xsmaxjdp, 0x00, 0x12, PPC2_ISA300),
-GEN_XX3FORM(xsminjdp, 0x00, 0x13, PPC2_ISA300),
GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300),
GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 3/4] target/ppc: fix xscvqpdp register access
2021-12-13 12:09 [PATCH v2 0/4] target/ppc: Fix VSX instructions register access Victor Colombo
2021-12-13 12:09 ` [PATCH v2 1/4] target/ppc: Fix xs{max, min}[cj]dp to use VSX registers Victor Colombo
2021-12-13 12:09 ` [PATCH v2 2/4] target/ppc: Move xs{max,min}[cj]dp to decodetree Victor Colombo
@ 2021-12-13 12:09 ` Victor Colombo
2021-12-13 12:09 ` [PATCH v2 4/4] target/ppc: move xscvqpdp to decodetree Victor Colombo
2021-12-15 16:50 ` [PATCH v2 0/4] target/ppc: Fix VSX instructions register access Cédric Le Goater
4 siblings, 0 replies; 6+ messages in thread
From: Victor Colombo @ 2021-12-13 12:09 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: danielhb413, richard.henderson, groug, victor.colombo, clg,
matheus.ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
This instruction has VRT and VRB fields instead of T/TX and B/BX.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/translate/vsx-impl.c.inc | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index e2447750dd..ab5cb21f13 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -913,8 +913,9 @@ static void gen_xscvqpdp(DisasContext *ctx)
return;
}
opc = tcg_const_i32(ctx->opcode);
- xt = gen_vsr_ptr(xT(ctx->opcode));
- xb = gen_vsr_ptr(xB(ctx->opcode));
+
+ xt = gen_vsr_ptr(rD(ctx->opcode) + 32);
+ xb = gen_vsr_ptr(rB(ctx->opcode) + 32);
gen_helper_xscvqpdp(cpu_env, opc, xt, xb);
tcg_temp_free_i32(opc);
tcg_temp_free_ptr(xt);
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 4/4] target/ppc: move xscvqpdp to decodetree
2021-12-13 12:09 [PATCH v2 0/4] target/ppc: Fix VSX instructions register access Victor Colombo
` (2 preceding siblings ...)
2021-12-13 12:09 ` [PATCH v2 3/4] target/ppc: fix xscvqpdp register access Victor Colombo
@ 2021-12-13 12:09 ` Victor Colombo
2021-12-15 16:50 ` [PATCH v2 0/4] target/ppc: Fix VSX instructions register access Cédric Le Goater
4 siblings, 0 replies; 6+ messages in thread
From: Victor Colombo @ 2021-12-13 12:09 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: danielhb413, richard.henderson, groug, victor.colombo, clg,
matheus.ferst, david
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/fpu_helper.c | 10 +++-------
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 4 ++++
target/ppc/translate/vsx-impl.c.inc | 24 +++++++++++++-----------
target/ppc/translate/vsx-ops.c.inc | 1 -
5 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index ad41ef1606..46f507604f 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2676,18 +2676,14 @@ VSX_CVT_FP_TO_FP_HP(xscvhpdp, 1, float16, float64, VsrH(3), VsrD(0), 1)
VSX_CVT_FP_TO_FP_HP(xvcvsphp, 4, float32, float16, VsrW(i), VsrH(2 * i + 1), 0)
VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, VsrH(2 * i + 1), VsrW(i), 0)
-/*
- * xscvqpdp isn't using VSX_CVT_FP_TO_FP() because xscvqpdpo will be
- * added to this later.
- */
-void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode,
- ppc_vsr_t *xt, ppc_vsr_t *xb)
+void helper_XSCVQPDP(CPUPPCState *env, uint32_t ro, ppc_vsr_t *xt,
+ ppc_vsr_t *xb)
{
ppc_vsr_t t = { };
float_status tstat;
tstat = env->fp_status;
- if (unlikely(Rc(opcode) != 0)) {
+ if (ro != 0) {
tstat.float_rounding_mode = float_round_to_odd;
}
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 12a3d5f269..ef5bdd38a7 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -400,7 +400,7 @@ DEF_HELPER_3(xscvdphp, void, env, vsr, vsr)
DEF_HELPER_4(xscvdpqp, void, env, i32, vsr, vsr)
DEF_HELPER_3(xscvdpsp, void, env, vsr, vsr)
DEF_HELPER_2(xscvdpspn, i64, env, i64)
-DEF_HELPER_4(xscvqpdp, void, env, i32, vsr, vsr)
+DEF_HELPER_4(XSCVQPDP, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscvqpsdz, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscvqpswz, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscvqpudz, void, env, i32, vsr, vsr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 759b2a9aa5..fd6bb13fa0 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -438,3 +438,7 @@ XSMAXCDP 111100 ..... ..... ..... 10000000 ... @XX3
XSMINCDP 111100 ..... ..... ..... 10001000 ... @XX3
XSMAXJDP 111100 ..... ..... ..... 10010000 ... @XX3
XSMINJDP 111100 ..... ..... ..... 10011000 ... @XX3
+
+## VSX Binary Floating-Point Convert Instructions
+
+XSCVQPDP 111111 ..... 10100 ..... 1101000100 . @X_tb_rc
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index ab5cb21f13..c08185e857 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -904,22 +904,24 @@ VSX_CMP(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
VSX_CMP(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
VSX_CMP(xvcmpnesp, 0x0C, 0x0B, 0, PPC2_VSX)
-static void gen_xscvqpdp(DisasContext *ctx)
+static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc *a)
{
- TCGv_i32 opc;
+ TCGv_i32 ro;
TCGv_ptr xt, xb;
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- opc = tcg_const_i32(ctx->opcode);
- xt = gen_vsr_ptr(rD(ctx->opcode) + 32);
- xb = gen_vsr_ptr(rB(ctx->opcode) + 32);
- gen_helper_xscvqpdp(cpu_env, opc, xt, xb);
- tcg_temp_free_i32(opc);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_VSX(ctx);
+
+ ro = tcg_const_i32(a->rc);
+
+ xt = gen_avr_ptr(a->rt);
+ xb = gen_avr_ptr(a->rb);
+ gen_helper_XSCVQPDP(cpu_env, ro, xt, xb);
+ tcg_temp_free_i32(ro);
tcg_temp_free_ptr(xt);
tcg_temp_free_ptr(xb);
+
+ return true;
}
#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index f980bc1bae..c974324c4c 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -133,7 +133,6 @@ GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
GEN_VSX_XFORM_300_EO(xscvdpqp, 0x04, 0x1A, 0x16, 0x00000001),
-GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0),
GEN_VSX_XFORM_300_EO(xscvqpsdz, 0x04, 0x1A, 0x19, 0x00000001),
GEN_VSX_XFORM_300_EO(xscvqpswz, 0x04, 0x1A, 0x09, 0x00000001),
GEN_VSX_XFORM_300_EO(xscvqpudz, 0x04, 0x1A, 0x11, 0x00000001),
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 0/4] target/ppc: Fix VSX instructions register access
2021-12-13 12:09 [PATCH v2 0/4] target/ppc: Fix VSX instructions register access Victor Colombo
` (3 preceding siblings ...)
2021-12-13 12:09 ` [PATCH v2 4/4] target/ppc: move xscvqpdp to decodetree Victor Colombo
@ 2021-12-15 16:50 ` Cédric Le Goater
4 siblings, 0 replies; 6+ messages in thread
From: Cédric Le Goater @ 2021-12-15 16:50 UTC (permalink / raw)
To: Victor Colombo, qemu-devel, qemu-ppc
Cc: matheus.ferst, danielhb413, richard.henderson, groug, david
On 12/13/21 13:09, Victor Colombo wrote:
> Instructions xscvqpdp, xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are
> using the wrong registers, which yields the wrong result when using
> them.
>
> This patch series fixes this issue by correcting the registers used.
> It also takes the opportunity to move these instructions to decodetree.
Applied to ppc-next.
Thanks,
C.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-12-15 17:15 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-12-13 12:09 [PATCH v2 0/4] target/ppc: Fix VSX instructions register access Victor Colombo
2021-12-13 12:09 ` [PATCH v2 1/4] target/ppc: Fix xs{max, min}[cj]dp to use VSX registers Victor Colombo
2021-12-13 12:09 ` [PATCH v2 2/4] target/ppc: Move xs{max,min}[cj]dp to decodetree Victor Colombo
2021-12-13 12:09 ` [PATCH v2 3/4] target/ppc: fix xscvqpdp register access Victor Colombo
2021-12-13 12:09 ` [PATCH v2 4/4] target/ppc: move xscvqpdp to decodetree Victor Colombo
2021-12-15 16:50 ` [PATCH v2 0/4] target/ppc: Fix VSX instructions register access Cédric Le Goater
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