From: "Rémi Denis-Courmont" <remi@remlab.net>
To: qemu-arm@nongnu.org
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH 14/14] target/arm: enable Secure EL2 in max CPU
Date: Tue, 03 Nov 2020 09:38:15 +0200 [thread overview]
Message-ID: <4572030.GXAFRqVoOG@basile.remlab.net> (raw)
In-Reply-To: <20201102105802.39332-14-remi.denis.courmont@huawei.com>
Le maanantaina 2. marraskuuta 2020, 12.58.02 EET
remi.denis.courmont@huawei.com a écrit :
> From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
>
> Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
> ---
> target/arm/cpu64.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 649213082f..8c3749268e 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -641,6 +641,7 @@ static void aarch64_max_initfn(Object *obj)
> t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
> t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
> t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
> + t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
> cpu->isar.id_aa64pfr0 = t;
>
> t = cpu->isar.id_aa64pfr1;
Answering my own patch as I have a policy question here...
This exposes SEL2 without TTST (small translation tables). On a logical level,
the two extensions are orthogonal. But per DDI0487, SEL2 implies TTST, so I am
not sure if this is considered an acceptable deviation in QEMU, or if
implementing TTST is deemed necessary.
Note that there's what seems like an editorial error in the spec: VSTCR
documentation covers the scenario that TTST is not supported by the CPU, even
though then VSTCR should not exist.
--
Реми Дёни-Курмон
http://www.remlab.net/
next prev parent reply other threads:[~2020-11-03 7:39 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <2172054.ElGaqSPkdT@basile.remlab.net>
2020-11-02 10:57 ` [PATCH 01/14] target/arm: add arm_is_el2_enabled() helper remi.denis.courmont
2020-11-02 11:06 ` Peter Maydell
2020-11-02 11:27 ` Peter Maydell
2020-11-02 13:35 ` Remi Denis Courmont
2020-11-03 16:42 ` Richard Henderson
2020-11-02 10:57 ` [PATCH 02/14] target/arm: use arm_is_el2_enabled() where applicable remi.denis.courmont
2020-11-03 16:53 ` Richard Henderson
2020-11-02 10:57 ` [PATCH 03/14] target/arm: use arm_hcr_el2_eff() " remi.denis.courmont
2020-11-03 16:56 ` Richard Henderson
2020-11-02 10:57 ` [PATCH 04/14] target/arm: factor MDCR_EL2 common handling remi.denis.courmont
2020-11-03 17:00 ` Richard Henderson
2020-11-02 10:57 ` [PATCH 05/14] target/arm: declare new AA64PFR0 bit-fields remi.denis.courmont
2020-11-03 17:02 ` Richard Henderson
2020-11-02 10:57 ` [PATCH 06/14] target/arm: add 64-bit S-EL2 to EL exception table remi.denis.courmont
2020-11-02 10:57 ` [PATCH 07/14] target/arm: return the stage 2 index for stage 1 remi.denis.courmont
2020-11-03 17:04 ` Richard Henderson
2020-11-02 10:57 ` [PATCH 08/14] target/arm: add MMU stage 1 for Secure EL2 remi.denis.courmont
2020-11-03 18:32 ` Richard Henderson
2020-11-03 18:49 ` Rémi Denis-Courmont
2020-11-03 19:41 ` Richard Henderson
2020-11-02 10:57 ` [PATCH 09/14] target/arm: add ARMv8.4-SEL2 system registers remi.denis.courmont
2020-11-03 19:49 ` Richard Henderson
2020-11-03 21:09 ` Peter Maydell
2020-11-03 21:40 ` Richard Henderson
2020-11-02 10:57 ` [PATCH 10/14] target/arm: do S1_ptw_translate() before address space lookup remi.denis.courmont
2020-11-03 19:54 ` Richard Henderson
2020-11-03 21:21 ` Rémi Denis-Courmont
2020-11-02 10:57 ` [PATCH 11/14] target/arm: secure stage 2 translation regime remi.denis.courmont
2020-11-02 10:58 ` [PATCH 12/14] target/arm: set HPFAR_EL2.NS on secure stage 2 faults remi.denis.courmont
2020-11-02 10:58 ` [PATCH 13/14] target/arm: add ARMv8.4-SEL2 extension remi.denis.courmont
2020-11-03 20:14 ` Richard Henderson
2020-11-02 10:58 ` [PATCH 14/14] target/arm: enable Secure EL2 in max CPU remi.denis.courmont
2020-11-03 7:38 ` Rémi Denis-Courmont [this message]
2020-11-03 16:38 ` Richard Henderson
2020-11-03 20:15 ` Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=4572030.GXAFRqVoOG@basile.remlab.net \
--to=remi@remlab.net \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).