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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id j1-20020a5d4481000000b002d2033ec465sm9249725wrq.36.2023.03.20.09.05.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Mar 2023 09:05:33 -0700 (PDT) Message-ID: <45961bdc-cd3a-c35a-8f10-bb9a52dd2e33@redhat.com> Date: Mon, 20 Mar 2023 17:05:31 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [RFC PATCH v2 06/11] hw/arm/smmuv3: Make TLB lookup work for stage-2 Content-Language: en-US To: Mostafa Saleh , qemu-devel@nongnu.org Cc: jean-philippe@linaro.org, peter.maydell@linaro.org, qemu-arm@nongnu.org, richard.henderson@linaro.org References: <20230226220650.1480786-1-smostafa@google.com> <20230226220650.1480786-7-smostafa@google.com> From: Eric Auger In-Reply-To: <20230226220650.1480786-7-smostafa@google.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Mostafa, On 2/26/23 23:06, Mostafa Saleh wrote: > Right now, either stage-1 or stage-2 are supported, this simplifies > how we can deal with TLBs. > This patch makes TLB lookup work if stage-2 is enabled instead of > stage-1. > TLB lookup is done before a PTW, if a valid entry is found we won't > do the PTW. > To be able to do TLB lookup, we need the correct tagging info, as > granularity and input size, so we get this based on the supported > translation stage. The TLB entries are added correctly from each > stage PTW. > > When nested translation is supported, this would need to change, for > example if we go with a combined TLB implementation, we would need to > use the min of the granularities in TLB. > > As stage-2 shouldn't be tagged by ASID, it will be set to -1 if S1P > is not enabled. > > Signed-off-by: Mostafa Saleh > --- > Changes in v2: > - check if S1 is enabled(not supported) when reading S1 TT. > --- > hw/arm/smmuv3.c | 45 ++++++++++++++++++++++++++++++++++----------- > 1 file changed, 34 insertions(+), 11 deletions(-) > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index dc74a5442d..ce193e9598 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -697,6 +697,9 @@ static int smmuv3_decode_config(IOMMUMemoryRegion *mr, SMMUTransCfg *cfg, > STE ste; > CD cd; > > + /* ASID defaults to -1 (if s1 is not supported). */ > + cfg->asid = -1; > + > ret = smmu_find_ste(s, sid, &ste, event); > if (ret) { > return ret; > @@ -787,6 +790,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, > SMMUTLBEntry *cached_entry = NULL; > SMMUTransTableInfo *tt; > SMMUTransCfg *cfg = NULL; > + uint8_t granule_sz, tsz; > IOMMUTLBEntry entry = { > .target_as = &address_space_memory, > .iova = addr, > @@ -822,21 +826,40 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, > goto epilogue; > } > > - tt = select_tt(cfg, addr); > - if (!tt) { > - if (cfg->record_faults) { > - event.type = SMMU_EVT_F_TRANSLATION; > - event.u.f_translation.addr = addr; > - event.u.f_translation.rnw = flag & 0x1; > + if (cfg->stage == 1) { > + /* Select stage1 translation table. */ > + tt = select_tt(cfg, addr); > + if (!tt) { > + if (cfg->record_faults) { > + event.type = SMMU_EVT_F_TRANSLATION; > + event.u.f_translation.addr = addr; > + event.u.f_translation.rnw = flag & 0x1; > + } > + status = SMMU_TRANS_ERROR; > + goto epilogue; > } > - status = SMMU_TRANS_ERROR; > - goto epilogue; > - } > + granule_sz = tt->granule_sz; > + tsz = tt->tsz; > > - page_mask = (1ULL << (tt->granule_sz)) - 1; > + } else { > + /* Stage2. */ > + granule_sz = cfg->s2cfg.granule_sz; > + tsz = cfg->s2cfg.tsz; > + } > + /* > + * TLB lookup looks for granule and input size for a translation stage, > + * as only one stage is supported right now, choose the right values > + * from the configuration. > + */ > + page_mask = (1ULL << granule_sz) - 1; > aligned_addr = addr & ~page_mask; > > - cached_entry = smmu_iotlb_lookup(bs, cfg, tt, aligned_addr); > + SMMUTransTableInfo temp = { Move the declaration at the top. Also rename temp into tt to be more explicit about what it is? > + .granule_sz = granule_sz, > + .tsz = tsz, > + }; > + > + cached_entry = smmu_iotlb_lookup(bs, cfg, &temp, aligned_addr); > if (cached_entry) { > if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) { > status = SMMU_TRANS_ERROR; Besides, looks good to me Reviewed-by: Eric Auger Thanks Eric