* [Qemu-devel] [PULL v2 01/11] MAINTAINERS: Add myself as openrisc maintainer
2017-05-04 0:53 [Qemu-devel] [PULL v2 00/11] Fixes and features for OpenRISC Stafford Horne
@ 2017-05-04 0:53 ` Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 02/11] target/openrisc: Implement EVBAR register Stafford Horne
` (10 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Stafford Horne @ 2017-05-04 0:53 UTC (permalink / raw)
To: QEMU Development; +Cc: Stefan Hajnoczi, Stafford Horne
Jia has claimed he is no longer able to maintain. I have fixing bugs here
and there and getting familiar with the code base. Orignal thread from Jia:
https://lists.librecores.org/pipermail/openrisc/2017-January/000321.html
Signed-off-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index c60235e..21803ca 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -196,8 +196,8 @@ F: hw/nios2/
F: disas/nios2.c
OpenRISC
-M: Jia Liu <proljc@gmail.com>
-S: Maintained
+M: Stafford Horne <shorne@gmail.com>
+S: Odd Fixes
F: target/openrisc/
F: hw/openrisc/
F: tests/tcg/openrisc/
--
2.9.3
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PULL v2 02/11] target/openrisc: Implement EVBAR register
2017-05-04 0:53 [Qemu-devel] [PULL v2 00/11] Fixes and features for OpenRISC Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 01/11] MAINTAINERS: Add myself as openrisc maintainer Stafford Horne
@ 2017-05-04 0:53 ` Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 03/11] target/openrisc: Implement EPH bit Stafford Horne
` (9 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Stafford Horne @ 2017-05-04 0:53 UTC (permalink / raw)
To: QEMU Development
Cc: Stefan Hajnoczi, Tim 'mithro' Ansell, Stafford Horne
From: Tim 'mithro' Ansell <mithro@mithis.com>
Exception Vector Base Address Register (EVBAR) - This optional register
can be used to apply an offset to the exception vector addresses.
The significant bits (31-12) of the vector offset address for each
exception depend on the setting of the Supervision Register (SR)'s EPH
bit and the Exception Vector Base Address Register (EVBAR).
Its presence is indicated by the EVBARP bit in the CPU Configuration
Register (CPUCFGR).
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/cpu.c | 2 ++
target/openrisc/cpu.h | 7 +++++++
target/openrisc/interrupt.c | 6 +++++-
target/openrisc/sys_helper.c | 7 +++++++
4 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 7fd2b9a..1524ed9 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -134,6 +134,7 @@ static void or1200_initfn(Object *obj)
set_feature(cpu, OPENRISC_FEATURE_OB32S);
set_feature(cpu, OPENRISC_FEATURE_OF32S);
+ set_feature(cpu, OPENRISC_FEATURE_EVBAR);
}
static void openrisc_any_initfn(Object *obj)
@@ -141,6 +142,7 @@ static void openrisc_any_initfn(Object *obj)
OpenRISCCPU *cpu = OPENRISC_CPU(obj);
set_feature(cpu, OPENRISC_FEATURE_OB32S);
+ set_feature(cpu, OPENRISC_FEATURE_EVBAR);
}
typedef struct OpenRISCCPUInfo {
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 418a0e6..1958b72 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -111,6 +111,11 @@ enum {
CPUCFGR_OF32S = (1 << 7),
CPUCFGR_OF64S = (1 << 8),
CPUCFGR_OV64S = (1 << 9),
+ /* CPUCFGR_ND = (1 << 10), */
+ /* CPUCFGR_AVRP = (1 << 11), */
+ CPUCFGR_EVBARP = (1 << 12),
+ /* CPUCFGR_ISRP = (1 << 13), */
+ /* CPUCFGR_AECSRP = (1 << 14), */
};
/* DMMU configure register */
@@ -200,6 +205,7 @@ enum {
OPENRISC_FEATURE_OF32S = (1 << 7),
OPENRISC_FEATURE_OF64S = (1 << 8),
OPENRISC_FEATURE_OV64S = (1 << 9),
+ OPENRISC_FEATURE_EVBAR = (1 << 12),
};
/* Tick Timer Mode Register */
@@ -289,6 +295,7 @@ typedef struct CPUOpenRISCState {
uint32_t dmmucfgr; /* DMMU configure register */
uint32_t immucfgr; /* IMMU configure register */
uint32_t esr; /* Exception supervisor register */
+ uint32_t evbar; /* Exception vector base address register */
uint32_t fpcsr; /* Float register */
float_status fp_status;
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index a2eec6f..78f0ba9 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -65,7 +65,11 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env->lock_addr = -1;
if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) {
- env->pc = (cs->exception_index << 8);
+ hwaddr vect_pc = cs->exception_index << 8;
+ if (env->cpucfgr & CPUCFGR_EVBARP) {
+ vect_pc |= env->evbar;
+ }
+ env->pc = vect_pc;
} else {
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
}
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 60c3193..6ba8162 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -39,6 +39,10 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
env->vr = rb;
break;
+ case TO_SPR(0, 11): /* EVBAR */
+ env->evbar = rb;
+ break;
+
case TO_SPR(0, 16): /* NPC */
cpu_restore_state(cs, GETPC());
/* ??? Mirror or1ksim in not trashing delayed branch state
@@ -206,6 +210,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
case TO_SPR(0, 4): /* IMMUCFGR */
return env->immucfgr;
+ case TO_SPR(0, 11): /* EVBAR */
+ return env->evbar;
+
case TO_SPR(0, 16): /* NPC (equals PC) */
cpu_restore_state(cs, GETPC());
return env->pc;
--
2.9.3
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PULL v2 03/11] target/openrisc: Implement EPH bit
2017-05-04 0:53 [Qemu-devel] [PULL v2 00/11] Fixes and features for OpenRISC Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 01/11] MAINTAINERS: Add myself as openrisc maintainer Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 02/11] target/openrisc: Implement EVBAR register Stafford Horne
@ 2017-05-04 0:53 ` Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 04/11] target/openrisc: Fixes for memory debugging Stafford Horne
` (8 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Stafford Horne @ 2017-05-04 0:53 UTC (permalink / raw)
To: QEMU Development
Cc: Stefan Hajnoczi, Tim 'mithro' Ansell, Stafford Horne
From: Tim 'mithro' Ansell <mithro@mithis.com>
Exception Prefix High (EPH) control bit of the Supervision Register
(SR).
The significant bits (31-12) of the vector offset address for each
exception depend on the setting of the Supervision Register (SR)'s EPH
bit and the Exception Vector Base Address Register (EVBAR).
If SR[EPH] is set, the vector offset is logically ORed with the offset
0xF0000000.
This means if EPH is;
* 0 - Exceptions vectors start at EVBAR
* 1 - Exception vectors start at EVBAR | 0xF0000000
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/interrupt.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index 78f0ba9..2c91fab 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -69,6 +69,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
if (env->cpucfgr & CPUCFGR_EVBARP) {
vect_pc |= env->evbar;
}
+ if (env->sr & SR_EPH) {
+ vect_pc |= 0xf0000000;
+ }
env->pc = vect_pc;
} else {
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
--
2.9.3
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PULL v2 04/11] target/openrisc: Fixes for memory debugging
2017-05-04 0:53 [Qemu-devel] [PULL v2 00/11] Fixes and features for OpenRISC Stafford Horne
` (2 preceding siblings ...)
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 03/11] target/openrisc: Implement EPH bit Stafford Horne
@ 2017-05-04 0:53 ` Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 05/11] target/openrisc: add numcores and coreid support Stafford Horne
` (7 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Stafford Horne @ 2017-05-04 0:53 UTC (permalink / raw)
To: QEMU Development; +Cc: Stefan Hajnoczi, Stafford Horne
When debugging in gdb you might want to inspect instructions in mapped
pages or in exception vectors like 0x800 etc. This was previously not
possible in qemu since the *get_phys_page_debug() routine only looked
into the data tlb.
Change to fall back to look into instruction tlb and plain physical
pages.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/mmu.c | 24 ++++++++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index 56b11d3..ce2a29d 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -124,7 +124,7 @@ static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu,
{
int ret = TLBRET_MATCH;
- if (rw == 2) { /* ITLB */
+ if (rw == MMU_INST_FETCH) { /* ITLB */
*physical = 0;
ret = cpu->env.tlb->cpu_openrisc_map_address_code(cpu, physical,
prot, address, rw);
@@ -221,12 +221,28 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
hwaddr phys_addr;
int prot;
+ int miss;
- if (cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0)) {
- return -1;
+ /* Check memory for any kind of address, since during debug the
+ gdb can ask for anything, check data tlb for address */
+ miss = cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0);
+
+ /* Check instruction tlb */
+ if (miss) {
+ miss = cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr,
+ MMU_INST_FETCH);
+ }
+
+ /* Last, fall back to a plain address */
+ if (miss) {
+ miss = cpu_openrisc_get_phys_nommu(cpu, &phys_addr, &prot, addr, 0);
}
- return phys_addr;
+ if (miss) {
+ return -1;
+ } else {
+ return phys_addr;
+ }
}
void cpu_openrisc_mmu_init(OpenRISCCPU *cpu)
--
2.9.3
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PULL v2 05/11] target/openrisc: add numcores and coreid support
2017-05-04 0:53 [Qemu-devel] [PULL v2 00/11] Fixes and features for OpenRISC Stafford Horne
` (3 preceding siblings ...)
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 04/11] target/openrisc: Fixes for memory debugging Stafford Horne
@ 2017-05-04 0:53 ` Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 06/11] migration: Add VMSTATE_UINTTL_2DARRAY() Stafford Horne
` (6 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Stafford Horne @ 2017-05-04 0:53 UTC (permalink / raw)
To: QEMU Development; +Cc: Stefan Hajnoczi, Stafford Horne
These are used to identify the processor in SMP system. Their
definition has been defined in verilog cores but it not yet part of the
spec but it will be soon.
The proposal for this is available:
https://openrisc.io/proposals/core-identifier-and-number-of-cores
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/sys_helper.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 6ba8162..e13666b 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -233,6 +233,12 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
case TO_SPR(0, 64): /* ESR */
return env->esr;
+ case TO_SPR(0, 128): /* COREID */
+ return 0;
+
+ case TO_SPR(0, 129): /* NUMCORES */
+ return 1;
+
case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
return env->tlb->dtlb[0][idx].mr;
--
2.9.3
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PULL v2 06/11] migration: Add VMSTATE_UINTTL_2DARRAY()
2017-05-04 0:53 [Qemu-devel] [PULL v2 00/11] Fixes and features for OpenRISC Stafford Horne
` (4 preceding siblings ...)
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 05/11] target/openrisc: add numcores and coreid support Stafford Horne
@ 2017-05-04 0:53 ` Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 07/11] target/openrisc: implement shadow registers Stafford Horne
` (5 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Stafford Horne @ 2017-05-04 0:53 UTC (permalink / raw)
To: QEMU Development; +Cc: Stefan Hajnoczi, Stafford Horne
In openRISC we are implementing the shadow registers as a 2d array.
Using this target long method rather than direct 32-bit alternatives is
consistent with the rest of our vm state serialization logic.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
include/migration/cpu.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/include/migration/cpu.h b/include/migration/cpu.h
index f3d5dfc..a40bd35 100644
--- a/include/migration/cpu.h
+++ b/include/migration/cpu.h
@@ -18,6 +18,8 @@
VMSTATE_UINT64_EQUAL_V(_f, _s, _v)
#define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \
VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v)
+#define VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, _v) \
+ VMSTATE_UINT64_2DARRAY_V(_f, _s, _n1, _n2, _v)
#define VMSTATE_UINTTL_TEST(_f, _s, _t) \
VMSTATE_UINT64_TEST(_f, _s, _t)
#define vmstate_info_uinttl vmstate_info_uint64
@@ -37,6 +39,8 @@
VMSTATE_UINT32_EQUAL_V(_f, _s, _v)
#define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \
VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v)
+#define VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, _v) \
+ VMSTATE_UINT32_2DARRAY_V(_f, _s, _n1, _n2, _v)
#define VMSTATE_UINTTL_TEST(_f, _s, _t) \
VMSTATE_UINT32_TEST(_f, _s, _t)
#define vmstate_info_uinttl vmstate_info_uint32
@@ -48,5 +52,8 @@
VMSTATE_UINTTL_EQUAL_V(_f, _s, 0)
#define VMSTATE_UINTTL_ARRAY(_f, _s, _n) \
VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, 0)
+#define VMSTATE_UINTTL_2DARRAY(_f, _s, _n1, _n2) \
+ VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, 0)
+
#endif
--
2.9.3
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PULL v2 07/11] target/openrisc: implement shadow registers
2017-05-04 0:53 [Qemu-devel] [PULL v2 00/11] Fixes and features for OpenRISC Stafford Horne
` (5 preceding siblings ...)
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 06/11] migration: Add VMSTATE_UINTTL_2DARRAY() Stafford Horne
@ 2017-05-04 0:53 ` Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 08/11] migration: Add VMSTATE_STRUCT_2DARRAY() Stafford Horne
` (4 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Stafford Horne @ 2017-05-04 0:53 UTC (permalink / raw)
To: QEMU Development; +Cc: Stefan Hajnoczi, Stafford Horne
Shadow registers are part of the openrisc spec along with sr[cid], as
part of the fast context switching feature. When exceptions occur,
instead of having to save registers to the stack if enabled the CID will
increment and a new set of registers will be available.
This patch only implements shadow registers which can be used as extra
scratch registers via the mfspr and mtspr if required. This is
implemented in a way where it would be easy to add on the fast context
switching, currently cid is hardcoded to 0.
This is need for openrisc linux smp kernels to boot correctly.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
linux-user/elfload.c | 2 +-
linux-user/main.c | 18 +++++++++---------
linux-user/openrisc/target_cpu.h | 6 +++---
linux-user/openrisc/target_signal.h | 2 +-
linux-user/signal.c | 17 +++++++++--------
target/openrisc/cpu.c | 4 +++-
target/openrisc/cpu.h | 15 +++++++++++++--
target/openrisc/gdbstub.c | 4 ++--
target/openrisc/machine.c | 6 +++---
target/openrisc/sys_helper.c | 9 +++++++++
target/openrisc/translate.c | 5 +++--
11 files changed, 56 insertions(+), 32 deletions(-)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index f520d77..ce77317 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1052,7 +1052,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs,
int i;
for (i = 0; i < 32; i++) {
- (*regs)[i] = tswapreg(env->gpr[i]);
+ (*regs)[i] = tswapreg(cpu_get_gpr(env, i));
}
(*regs)[32] = tswapreg(env->pc);
(*regs)[33] = tswapreg(cpu_get_sr(env));
diff --git a/linux-user/main.c b/linux-user/main.c
index 10a3bb3..79d621b 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -2590,17 +2590,17 @@ void cpu_loop(CPUOpenRISCState *env)
case EXCP_SYSCALL:
env->pc += 4; /* 0xc00; */
ret = do_syscall(env,
- env->gpr[11], /* return value */
- env->gpr[3], /* r3 - r7 are params */
- env->gpr[4],
- env->gpr[5],
- env->gpr[6],
- env->gpr[7],
- env->gpr[8], 0, 0);
+ cpu_get_gpr(env, 11), /* return value */
+ cpu_get_gpr(env, 3), /* r3 - r7 are params */
+ cpu_get_gpr(env, 4),
+ cpu_get_gpr(env, 5),
+ cpu_get_gpr(env, 6),
+ cpu_get_gpr(env, 7),
+ cpu_get_gpr(env, 8), 0, 0);
if (ret == -TARGET_ERESTARTSYS) {
env->pc -= 4;
} else if (ret != -TARGET_QEMU_ESIGRETURN) {
- env->gpr[11] = ret;
+ cpu_set_gpr(env, 11, ret);
}
break;
case EXCP_DPF:
@@ -4765,7 +4765,7 @@ int main(int argc, char **argv, char **envp)
int i;
for (i = 0; i < 32; i++) {
- env->gpr[i] = regs->gpr[i];
+ cpu_set_gpr(env, i, regs->gpr[i]);
}
env->pc = regs->pc;
cpu_set_sr(env, regs->sr);
diff --git a/linux-user/openrisc/target_cpu.h b/linux-user/openrisc/target_cpu.h
index f283d96..606ad6f 100644
--- a/linux-user/openrisc/target_cpu.h
+++ b/linux-user/openrisc/target_cpu.h
@@ -23,14 +23,14 @@
static inline void cpu_clone_regs(CPUOpenRISCState *env, target_ulong newsp)
{
if (newsp) {
- env->gpr[1] = newsp;
+ cpu_set_gpr(env, 1, newsp);
}
- env->gpr[11] = 0;
+ cpu_set_gpr(env, 11, 0);
}
static inline void cpu_set_tls(CPUOpenRISCState *env, target_ulong newtls)
{
- env->gpr[10] = newtls;
+ cpu_set_gpr(env, 10, newtls);
}
#endif
diff --git a/linux-user/openrisc/target_signal.h b/linux-user/openrisc/target_signal.h
index 9f2c493..95a733e 100644
--- a/linux-user/openrisc/target_signal.h
+++ b/linux-user/openrisc/target_signal.h
@@ -20,7 +20,7 @@ typedef struct target_sigaltstack {
static inline abi_ulong get_sp_from_cpustate(CPUOpenRISCState *state)
{
- return state->gpr[1];
+ return cpu_get_gpr(state, 1);
}
diff --git a/linux-user/signal.c b/linux-user/signal.c
index a67db04..3d18d1b 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -4411,7 +4411,7 @@ static void setup_sigcontext(struct target_sigcontext *sc,
CPUOpenRISCState *regs,
unsigned long mask)
{
- unsigned long usp = regs->gpr[1];
+ unsigned long usp = cpu_get_gpr(regs, 1);
/* copy the regs. they are first in sc so we can use sc directly */
@@ -4436,7 +4436,7 @@ static inline abi_ulong get_sigframe(struct target_sigaction *ka,
CPUOpenRISCState *regs,
size_t frame_size)
{
- unsigned long sp = regs->gpr[1];
+ unsigned long sp = cpu_get_gpr(regs, 1);
int onsigstack = on_sig_stack(sp);
/* redzone */
@@ -4489,7 +4489,8 @@ static void setup_rt_frame(int sig, struct target_sigaction *ka,
__put_user(0, &frame->uc.tuc_link);
__put_user(target_sigaltstack_used.ss_sp,
&frame->uc.tuc_stack.ss_sp);
- __put_user(sas_ss_flags(env->gpr[1]), &frame->uc.tuc_stack.ss_flags);
+ __put_user(sas_ss_flags(cpu_get_gpr(env, 1)),
+ &frame->uc.tuc_stack.ss_flags);
__put_user(target_sigaltstack_used.ss_size,
&frame->uc.tuc_stack.ss_size);
setup_sigcontext(&frame->sc, env, set->sig[0]);
@@ -4512,13 +4513,13 @@ static void setup_rt_frame(int sig, struct target_sigaction *ka,
/* Set up registers for signal handler */
env->pc = (unsigned long)ka->_sa_handler; /* what we enter NOW */
- env->gpr[9] = (unsigned long)return_ip; /* what we enter LATER */
- env->gpr[3] = (unsigned long)sig; /* arg 1: signo */
- env->gpr[4] = (unsigned long)&frame->info; /* arg 2: (siginfo_t*) */
- env->gpr[5] = (unsigned long)&frame->uc; /* arg 3: ucontext */
+ cpu_set_gpr(env, 9, (unsigned long)return_ip); /* what we enter LATER */
+ cpu_set_gpr(env, 3, (unsigned long)sig); /* arg 1: signo */
+ cpu_set_gpr(env, 4, (unsigned long)&frame->info); /* arg 2: (siginfo_t*) */
+ cpu_set_gpr(env, 5, (unsigned long)&frame->uc); /* arg 3: ucontext */
/* actually move the usp to reflect the stacked frame */
- env->gpr[1] = (unsigned long)frame;
+ cpu_set_gpr(env, 1, (unsigned long)frame);
return;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 1524ed9..6c1ed07 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -52,7 +52,7 @@ static void openrisc_cpu_reset(CPUState *s)
s->exception_index = -1;
cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
- cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S;
+ cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S | CPUCFGR_NSGF;
cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
@@ -132,6 +132,7 @@ static void or1200_initfn(Object *obj)
{
OpenRISCCPU *cpu = OPENRISC_CPU(obj);
+ set_feature(cpu, OPENRISC_FEATURE_NSGF);
set_feature(cpu, OPENRISC_FEATURE_OB32S);
set_feature(cpu, OPENRISC_FEATURE_OF32S);
set_feature(cpu, OPENRISC_FEATURE_EVBAR);
@@ -141,6 +142,7 @@ static void openrisc_any_initfn(Object *obj)
{
OpenRISCCPU *cpu = OPENRISC_CPU(obj);
+ set_feature(cpu, OPENRISC_FEATURE_NSGF);
set_feature(cpu, OPENRISC_FEATURE_OB32S);
set_feature(cpu, OPENRISC_FEATURE_EVBAR);
}
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 1958b72..e159b22 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -275,7 +275,8 @@ typedef struct CPUOpenRISCTLBContext {
#endif
typedef struct CPUOpenRISCState {
- target_ulong gpr[32]; /* General registers */
+ target_ulong shadow_gpr[16][32]; /* Shadow registers */
+
target_ulong pc; /* Program counter */
target_ulong ppc; /* Prev PC */
target_ulong jmp_pc; /* Jump PC */
@@ -399,6 +400,16 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
#define TB_FLAGS_R0_0 2
#define TB_FLAGS_OVE SR_OVE
+static inline uint32_t cpu_get_gpr(const CPUOpenRISCState *env, int i)
+{
+ return env->shadow_gpr[0][i];
+}
+
+static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val)
+{
+ env->shadow_gpr[0][i] = val;
+}
+
static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
@@ -406,7 +417,7 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
*pc = env->pc;
*cs_base = 0;
*flags = (env->dflag
- | (env->gpr[0] == 0 ? TB_FLAGS_R0_0 : 0)
+ | (cpu_get_gpr(env, 0) == 0 ? TB_FLAGS_R0_0 : 0)
| (env->sr & SR_OVE));
}
diff --git a/target/openrisc/gdbstub.c b/target/openrisc/gdbstub.c
index b18c7e9..f9af650 100644
--- a/target/openrisc/gdbstub.c
+++ b/target/openrisc/gdbstub.c
@@ -28,7 +28,7 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
CPUOpenRISCState *env = &cpu->env;
if (n < 32) {
- return gdb_get_reg32(mem_buf, env->gpr[n]);
+ return gdb_get_reg32(mem_buf, cpu_get_gpr(env, n));
} else {
switch (n) {
case 32: /* PPC */
@@ -61,7 +61,7 @@ int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
tmp = ldl_p(mem_buf);
if (n < 32) {
- env->gpr[n] = tmp;
+ cpu_set_gpr(env, n, tmp);
} else {
switch (n) {
case 32: /* PPC */
diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c
index 686eaa3..2bf71c3 100644
--- a/target/openrisc/machine.c
+++ b/target/openrisc/machine.c
@@ -47,10 +47,10 @@ static const VMStateInfo vmstate_sr = {
static const VMStateDescription vmstate_env = {
.name = "env",
- .version_id = 4,
- .minimum_version_id = 4,
+ .version_id = 5,
+ .minimum_version_id = 5,
.fields = (VMStateField[]) {
- VMSTATE_UINTTL_ARRAY(gpr, CPUOpenRISCState, 32),
+ VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32),
VMSTATE_UINTTL(pc, CPUOpenRISCState),
VMSTATE_UINTTL(ppc, CPUOpenRISCState),
VMSTATE_UINTTL(jmp_pc, CPUOpenRISCState),
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index e13666b..fa3d6a4 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -92,6 +92,11 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
case TO_SPR(0, 64): /* ESR */
env->esr = rb;
break;
+
+ case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
+ idx = (spr - 1024);
+ env->shadow_gpr[idx / 32][idx % 32] = rb;
+
case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
if (!(rb & 1)) {
@@ -239,6 +244,10 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
case TO_SPR(0, 129): /* NUMCORES */
return 1;
+ case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
+ idx = (spr - 1024);
+ return env->shadow_gpr[idx / 32][idx % 32];
+
case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
return env->tlb->dtlb[0][idx].mr;
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 7c4cbf2..e49518e 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -107,7 +107,8 @@ void openrisc_translate_init(void)
"mac");
for (i = 0; i < 32; i++) {
cpu_R[i] = tcg_global_mem_new(cpu_env,
- offsetof(CPUOpenRISCState, gpr[i]),
+ offsetof(CPUOpenRISCState,
+ shadow_gpr[0][i]),
regnames[i]);
}
cpu_R0 = cpu_R[0];
@@ -1662,7 +1663,7 @@ void openrisc_cpu_dump_state(CPUState *cs, FILE *f,
cpu_fprintf(f, "PC=%08x\n", env->pc);
for (i = 0; i < 32; ++i) {
- cpu_fprintf(f, "R%02d=%08x%c", i, env->gpr[i],
+ cpu_fprintf(f, "R%02d=%08x%c", i, cpu_get_gpr(env, i),
(i % 4) == 3 ? '\n' : ' ');
}
}
--
2.9.3
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PULL v2 08/11] migration: Add VMSTATE_STRUCT_2DARRAY()
2017-05-04 0:53 [Qemu-devel] [PULL v2 00/11] Fixes and features for OpenRISC Stafford Horne
` (6 preceding siblings ...)
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 07/11] target/openrisc: implement shadow registers Stafford Horne
@ 2017-05-04 0:53 ` Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 09/11] target/openrisc: Implement full vmstate serialization Stafford Horne
` (3 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Stafford Horne @ 2017-05-04 0:53 UTC (permalink / raw)
To: QEMU Development; +Cc: Stefan Hajnoczi, Stafford Horne
For openrisc we implement tlb state as a 2d array of tlb entry structs.
This is added to allow easy storing of state of 2d arrays.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
include/migration/vmstate.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index f2dbf84..4834e55 100644
--- a/include/migration/vmstate.h
+++ b/include/migration/vmstate.h
@@ -499,6 +499,19 @@ extern const VMStateInfo vmstate_info_qtailq;
.offset = vmstate_offset_array(_state, _field, _type, _num),\
}
+#define VMSTATE_STRUCT_2DARRAY_TEST(_field, _state, _n1, _n2, _test, \
+ _version, _vmsd, _type) { \
+ .name = (stringify(_field)), \
+ .num = (_n1) * (_n2), \
+ .field_exists = (_test), \
+ .version_id = (_version), \
+ .vmsd = &(_vmsd), \
+ .size = sizeof(_type), \
+ .flags = VMS_STRUCT | VMS_ARRAY, \
+ .offset = vmstate_offset_2darray(_state, _field, _type, \
+ _n1, _n2), \
+}
+
#define VMSTATE_STRUCT_VARRAY_UINT8(_field, _state, _field_num, _version, _vmsd, _type) { \
.name = (stringify(_field)), \
.num_offset = vmstate_offset_value(_state, _field_num, uint8_t), \
@@ -746,6 +759,11 @@ extern const VMStateInfo vmstate_info_qtailq;
VMSTATE_STRUCT_ARRAY_TEST(_field, _state, _num, NULL, _version, \
_vmsd, _type)
+#define VMSTATE_STRUCT_2DARRAY(_field, _state, _n1, _n2, _version, \
+ _vmsd, _type) \
+ VMSTATE_STRUCT_2DARRAY_TEST(_field, _state, _n1, _n2, NULL, \
+ _version, _vmsd, _type)
+
#define VMSTATE_BUFFER_UNSAFE_INFO(_field, _state, _version, _info, _size) \
VMSTATE_BUFFER_UNSAFE_INFO_TEST(_field, _state, NULL, _version, _info, \
_size)
--
2.9.3
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PULL v2 09/11] target/openrisc: Implement full vmstate serialization
2017-05-04 0:53 [Qemu-devel] [PULL v2 00/11] Fixes and features for OpenRISC Stafford Horne
` (7 preceding siblings ...)
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 08/11] migration: Add VMSTATE_STRUCT_2DARRAY() Stafford Horne
@ 2017-05-04 0:53 ` Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 10/11] target/openrisc: Remove duplicate features property Stafford Horne
` (2 subsequent siblings)
11 siblings, 0 replies; 13+ messages in thread
From: Stafford Horne @ 2017-05-04 0:53 UTC (permalink / raw)
To: QEMU Development; +Cc: Stefan Hajnoczi, Stafford Horne
Previously serialization did not persist the tlb, timer, pic and other
key state items. This meant snapshotting and restoring a running os
would crash. After adding these I am able to take snapshots of a
running linux os and restore at a later time.
I am currently not trying to maintain capatibility with older versions
as I do not believe this really worked before or anyone used it.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/machine.c | 73 +++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 71 insertions(+), 2 deletions(-)
diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c
index 2bf71c3..a82be62 100644
--- a/target/openrisc/machine.c
+++ b/target/openrisc/machine.c
@@ -24,6 +24,63 @@
#include "hw/boards.h"
#include "migration/cpu.h"
+static int env_post_load(void *opaque, int version_id)
+{
+ CPUOpenRISCState *env = opaque;
+
+ /* Restore MMU handlers */
+ if (env->sr & SR_DME) {
+ env->tlb->cpu_openrisc_map_address_data =
+ &cpu_openrisc_get_phys_data;
+ } else {
+ env->tlb->cpu_openrisc_map_address_data =
+ &cpu_openrisc_get_phys_nommu;
+ }
+
+ if (env->sr & SR_IME) {
+ env->tlb->cpu_openrisc_map_address_code =
+ &cpu_openrisc_get_phys_code;
+ } else {
+ env->tlb->cpu_openrisc_map_address_code =
+ &cpu_openrisc_get_phys_nommu;
+ }
+
+
+ return 0;
+}
+
+static const VMStateDescription vmstate_tlb_entry = {
+ .name = "tlb_entry",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(mr, OpenRISCTLBEntry),
+ VMSTATE_UINTTL(tr, OpenRISCTLBEntry),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_cpu_tlb = {
+ .name = "cpu_tlb",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT_2DARRAY(itlb, CPUOpenRISCTLBContext,
+ ITLB_WAYS, ITLB_SIZE, 0,
+ vmstate_tlb_entry, OpenRISCTLBEntry),
+ VMSTATE_STRUCT_2DARRAY(dtlb, CPUOpenRISCTLBContext,
+ DTLB_WAYS, DTLB_SIZE, 0,
+ vmstate_tlb_entry, OpenRISCTLBEntry),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+#define VMSTATE_CPU_TLB(_f, _s) \
+ VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_tlb, CPUOpenRISCTLBContext)
+
+
static int get_sr(QEMUFile *f, void *opaque, size_t size, VMStateField *field)
{
CPUOpenRISCState *env = opaque;
@@ -47,8 +104,9 @@ static const VMStateInfo vmstate_sr = {
static const VMStateDescription vmstate_env = {
.name = "env",
- .version_id = 5,
- .minimum_version_id = 5,
+ .version_id = 6,
+ .minimum_version_id = 6,
+ .post_load = env_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32),
VMSTATE_UINTTL(pc, CPUOpenRISCState),
@@ -79,9 +137,20 @@ static const VMStateDescription vmstate_env = {
VMSTATE_UINT32(cpucfgr, CPUOpenRISCState),
VMSTATE_UINT32(dmmucfgr, CPUOpenRISCState),
VMSTATE_UINT32(immucfgr, CPUOpenRISCState),
+ VMSTATE_UINT32(evbar, CPUOpenRISCState),
VMSTATE_UINT32(esr, CPUOpenRISCState),
VMSTATE_UINT32(fpcsr, CPUOpenRISCState),
VMSTATE_UINT64(mac, CPUOpenRISCState),
+
+ VMSTATE_CPU_TLB(tlb, CPUOpenRISCState),
+
+ VMSTATE_TIMER_PTR(timer, CPUOpenRISCState),
+ VMSTATE_UINT32(ttmr, CPUOpenRISCState),
+ VMSTATE_UINT32(ttcr, CPUOpenRISCState),
+
+ VMSTATE_UINT32(picmr, CPUOpenRISCState),
+ VMSTATE_UINT32(picsr, CPUOpenRISCState),
+
VMSTATE_END_OF_LIST()
}
};
--
2.9.3
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PULL v2 10/11] target/openrisc: Remove duplicate features property
2017-05-04 0:53 [Qemu-devel] [PULL v2 00/11] Fixes and features for OpenRISC Stafford Horne
` (8 preceding siblings ...)
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 09/11] target/openrisc: Implement full vmstate serialization Stafford Horne
@ 2017-05-04 0:53 ` Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 11/11] target/openrisc: Support non-busy idle state using PMR SPR Stafford Horne
2017-05-05 15:29 ` [Qemu-devel] [PULL v2 00/11] Fixes and features for OpenRISC Stefan Hajnoczi
11 siblings, 0 replies; 13+ messages in thread
From: Stafford Horne @ 2017-05-04 0:53 UTC (permalink / raw)
To: QEMU Development; +Cc: Stefan Hajnoczi, Stafford Horne
The features property has stored the exact same thing as the cpucfgr
spr. Remove the feature enum and property as it is not needed.
In order to preserve the behavior or keeping features accross reset this
patch moves cpucfgr into the non reset region of the state struct. Since
the cpucfgr is read only this means we only need to sset cpucfgr once
during class init.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/cpu.c | 17 +++--------------
target/openrisc/cpu.h | 16 ++--------------
2 files changed, 5 insertions(+), 28 deletions(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 6c1ed07..c9b3f22 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -52,7 +52,6 @@ static void openrisc_cpu_reset(CPUState *s)
s->exception_index = -1;
cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
- cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S | CPUCFGR_NSGF;
cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
@@ -65,12 +64,6 @@ static void openrisc_cpu_reset(CPUState *s)
#endif
}
-static inline void set_feature(OpenRISCCPU *cpu, int feature)
-{
- cpu->feature |= feature;
- cpu->env.cpucfgr = cpu->feature;
-}
-
static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
@@ -132,19 +125,15 @@ static void or1200_initfn(Object *obj)
{
OpenRISCCPU *cpu = OPENRISC_CPU(obj);
- set_feature(cpu, OPENRISC_FEATURE_NSGF);
- set_feature(cpu, OPENRISC_FEATURE_OB32S);
- set_feature(cpu, OPENRISC_FEATURE_OF32S);
- set_feature(cpu, OPENRISC_FEATURE_EVBAR);
+ cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
+ CPUCFGR_EVBARP;
}
static void openrisc_any_initfn(Object *obj)
{
OpenRISCCPU *cpu = OPENRISC_CPU(obj);
- set_feature(cpu, OPENRISC_FEATURE_NSGF);
- set_feature(cpu, OPENRISC_FEATURE_OB32S);
- set_feature(cpu, OPENRISC_FEATURE_EVBAR);
+ cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP;
}
typedef struct OpenRISCCPUInfo {
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index e159b22..938ccc3 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -196,18 +196,6 @@ enum {
SR_SCE = (1 << 17),
};
-/* OpenRISC Hardware Capabilities */
-enum {
- OPENRISC_FEATURE_NSGF = (15 << 0),
- OPENRISC_FEATURE_CGF = (1 << 4),
- OPENRISC_FEATURE_OB32S = (1 << 5),
- OPENRISC_FEATURE_OB64S = (1 << 6),
- OPENRISC_FEATURE_OF32S = (1 << 7),
- OPENRISC_FEATURE_OF64S = (1 << 8),
- OPENRISC_FEATURE_OV64S = (1 << 9),
- OPENRISC_FEATURE_EVBAR = (1 << 12),
-};
-
/* Tick Timer Mode Register */
enum {
TTMR_TP = (0xfffffff),
@@ -292,7 +280,6 @@ typedef struct CPUOpenRISCState {
uint32_t sr; /* Supervisor register, without SR_{F,CY,OV} */
uint32_t vr; /* Version register */
uint32_t upr; /* Unit presence register */
- uint32_t cpucfgr; /* CPU configure register */
uint32_t dmmucfgr; /* DMMU configure register */
uint32_t immucfgr; /* IMMU configure register */
uint32_t esr; /* Exception supervisor register */
@@ -311,6 +298,8 @@ typedef struct CPUOpenRISCState {
CPU_COMMON
/* Fields from here on are preserved across CPU reset. */
+ uint32_t cpucfgr; /* CPU configure register */
+
#ifndef CONFIG_USER_ONLY
CPUOpenRISCTLBContext * tlb;
@@ -337,7 +326,6 @@ typedef struct OpenRISCCPU {
CPUOpenRISCState env;
- uint32_t feature; /* CPU Capabilities */
} OpenRISCCPU;
static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env)
--
2.9.3
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PULL v2 11/11] target/openrisc: Support non-busy idle state using PMR SPR
2017-05-04 0:53 [Qemu-devel] [PULL v2 00/11] Fixes and features for OpenRISC Stafford Horne
` (9 preceding siblings ...)
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 10/11] target/openrisc: Remove duplicate features property Stafford Horne
@ 2017-05-04 0:53 ` Stafford Horne
2017-05-05 15:29 ` [Qemu-devel] [PULL v2 00/11] Fixes and features for OpenRISC Stefan Hajnoczi
11 siblings, 0 replies; 13+ messages in thread
From: Stafford Horne @ 2017-05-04 0:53 UTC (permalink / raw)
To: QEMU Development; +Cc: Stefan Hajnoczi, Stafford Horne
The OpenRISC architecture has the Power Management Register (PMR)
special purpose register to manage cpu power states. The interesting
modes are:
* Doze Mode (DME) - Stop cpu except timer & pic - wake on interrupt
* Sleep Mode (SME) - Stop cpu and all units - wake on interrupt
* Suspend Model (SUME) - Stop cpu and all units - wake on reset
The linux kernel will set DME when idle.
This patch implements the PMR SPR and halts the qemu cpu when there is a
change to DME or SME. This means that openrisc qemu in no longer peggs
a host cpu at 100%.
In order for this to work we need to kick the CPU when timers are
expired. Update the cpu timer to kick the cpu upon each timer event.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
hw/openrisc/cputimer.c | 1 +
target/openrisc/cpu.c | 3 ++-
target/openrisc/cpu.h | 10 ++++++++++
target/openrisc/interrupt.c | 2 ++
target/openrisc/machine.c | 1 +
target/openrisc/sys_helper.c | 13 +++++++++++++
6 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c
index a98c799..febc469 100644
--- a/hw/openrisc/cputimer.c
+++ b/hw/openrisc/cputimer.c
@@ -61,6 +61,7 @@ void cpu_openrisc_timer_update(OpenRISCCPU *cpu)
}
next = now + (uint64_t)wait * TIMER_PERIOD;
timer_mod(cpu->env.timer, next);
+ qemu_cpu_kick(CPU(cpu));
}
void cpu_openrisc_count_start(OpenRISCCPU *cpu)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index c9b3f22..1d6330c 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -51,7 +51,8 @@ static void openrisc_cpu_reset(CPUState *s)
cpu->env.lock_addr = -1;
s->exception_index = -1;
- cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
+ cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP |
+ UPR_PMP;
cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 938ccc3..2721432 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -140,6 +140,15 @@ enum {
IMMUCFGR_HTR = (1 << 11),
};
+/* Power management register */
+enum {
+ PMR_SDF = (15 << 0),
+ PMR_DME = (1 << 4),
+ PMR_SME = (1 << 5),
+ PMR_DCGE = (1 << 6),
+ PMR_SUME = (1 << 7),
+};
+
/* Float point control status register */
enum {
FPCSR_FPEE = 1,
@@ -284,6 +293,7 @@ typedef struct CPUOpenRISCState {
uint32_t immucfgr; /* IMMU configure register */
uint32_t esr; /* Exception supervisor register */
uint32_t evbar; /* Exception vector base address register */
+ uint32_t pmr; /* Power Management Register */
uint32_t fpcsr; /* Float register */
float_status fp_status;
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index 2c91fab..3959671 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -60,6 +60,8 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env->sr |= SR_SM;
env->sr &= ~SR_IEE;
env->sr &= ~SR_TEE;
+ env->pmr &= ~PMR_DME;
+ env->pmr &= ~PMR_SME;
env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
env->lock_addr = -1;
diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c
index a82be62..a20cce7 100644
--- a/target/openrisc/machine.c
+++ b/target/openrisc/machine.c
@@ -138,6 +138,7 @@ static const VMStateDescription vmstate_env = {
VMSTATE_UINT32(dmmucfgr, CPUOpenRISCState),
VMSTATE_UINT32(immucfgr, CPUOpenRISCState),
VMSTATE_UINT32(evbar, CPUOpenRISCState),
+ VMSTATE_UINT32(pmr, CPUOpenRISCState),
VMSTATE_UINT32(esr, CPUOpenRISCState),
VMSTATE_UINT32(fpcsr, CPUOpenRISCState),
VMSTATE_UINT64(mac, CPUOpenRISCState),
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index fa3d6a4..abdef5d 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -22,6 +22,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
+#include "exception.h"
#define TO_SPR(group, number) (((group) << 11) + (number))
@@ -141,6 +142,15 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
case TO_SPR(5, 2): /* MACHI */
env->mac = deposit64(env->mac, 32, 32, rb);
break;
+ case TO_SPR(8, 0): /* PMR */
+ env->pmr = rb;
+ if (env->pmr & PMR_DME || env->pmr & PMR_SME) {
+ cpu_restore_state(cs, GETPC());
+ env->pc += 4;
+ cs->halted = 1;
+ raise_exception(cpu, EXCP_HALTED);
+ }
+ break;
case TO_SPR(9, 0): /* PICMR */
env->picmr |= rb;
break;
@@ -287,6 +297,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
return env->mac >> 32;
break;
+ case TO_SPR(8, 0): /* PMR */
+ return env->pmr;
+
case TO_SPR(9, 0): /* PICMR */
return env->picmr;
--
2.9.3
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PULL v2 00/11] Fixes and features for OpenRISC
2017-05-04 0:53 [Qemu-devel] [PULL v2 00/11] Fixes and features for OpenRISC Stafford Horne
` (10 preceding siblings ...)
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 11/11] target/openrisc: Support non-busy idle state using PMR SPR Stafford Horne
@ 2017-05-05 15:29 ` Stefan Hajnoczi
11 siblings, 0 replies; 13+ messages in thread
From: Stefan Hajnoczi @ 2017-05-05 15:29 UTC (permalink / raw)
To: Stafford Horne; +Cc: QEMU Development
[-- Attachment #1: Type: text/plain, Size: 2924 bytes --]
On Thu, May 04, 2017 at 09:53:15AM +0900, Stafford Horne wrote:
> Hello,
>
> This are the openrisc patches I have been circulating on the mailing list
> of the last few months. We have had help from a few new people and added
> the following:
> * Fixes for gdb memory debugging
> * Added support for Shadow Registers, EVBAR, EPH
> * Added support for idle state, no more 100% pegged cpu's
> * Fixed VM state persisting
>
>
> Changes Since v1:
> o Fixed all checkpatch warnings and errors
>
>
> The following changes since commit 359c41abe32638adad503e386969fa428cecff52:
>
> Update version for v2.9.0 release (2017-04-20 15:31:34 +0100)
>
> are available in the git repository at:
>
> git://github.com/stffrdhrn/qemu.git tags/pull-or-20170504
>
> for you to fetch changes up to f4d1414a9385e3375d9107b29eeb75d27daf2147:
>
> target/openrisc: Support non-busy idle state using PMR SPR (2017-05-04 09:39:14 +0900)
>
> ----------------------------------------------------------------
> Openrisc Features and Fixes for qemu 2.10
>
> ----------------------------------------------------------------
> Stafford Horne (9):
> MAINTAINERS: Add myself as openrisc maintainer
> target/openrisc: Fixes for memory debugging
> target/openrisc: add numcores and coreid support
> migration: Add VMSTATE_UINTTL_2DARRAY()
> target/openrisc: implement shadow registers
> migration: Add VMSTATE_STRUCT_2DARRAY()
> target/openrisc: Implement full vmstate serialization
> target/openrisc: Remove duplicate features property
> target/openrisc: Support non-busy idle state using PMR SPR
>
> Tim 'mithro' Ansell (2):
> target/openrisc: Implement EVBAR register
> target/openrisc: Implement EPH bit
>
> MAINTAINERS | 4 +-
> hw/openrisc/cputimer.c | 1 +
> include/migration/cpu.h | 7 ++++
> include/migration/vmstate.h | 18 +++++++++
> linux-user/elfload.c | 2 +-
> linux-user/main.c | 18 ++++-----
> linux-user/openrisc/target_cpu.h | 6 +--
> linux-user/openrisc/target_signal.h | 2 +-
> linux-user/signal.c | 17 +++++----
> target/openrisc/cpu.c | 16 +++-----
> target/openrisc/cpu.h | 46 ++++++++++++++--------
> target/openrisc/gdbstub.c | 4 +-
> target/openrisc/interrupt.c | 11 +++++-
> target/openrisc/machine.c | 76 +++++++++++++++++++++++++++++++++++--
> target/openrisc/mmu.c | 24 ++++++++++--
> target/openrisc/sys_helper.c | 35 +++++++++++++++++
> target/openrisc/translate.c | 5 ++-
> 17 files changed, 230 insertions(+), 62 deletions(-)
>
> --
> 2.9.3
>
Thanks, applied to my staging tree:
https://github.com/stefanha/qemu/commits/staging
Stefan
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 455 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread