From: Dirk Behme <dirk.behme@googlemail.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] Decode of MIPS DMFC0 and DMTC0
Date: Wed, 10 Jan 2007 21:32:45 +0100 [thread overview]
Message-ID: <45A54D6D.8040803@googlemail.com> (raw)
Hi,
looking into target-mips/translate.c, in function
decode_opc() OPC_DMFC0 and OPC_DMTC0 are mapped to gen_cp0()
if MIPS64 is enabled:
case OPC_CP0:
op1 = MASK_CP0(ctx->opcode);
switch (op1) {
case OPC_MFC0:
case OPC_MTC0:
#ifdef MIPS_HAS_MIPS64
case OPC_DMFC0:
case OPC_DMTC0:
#endif
gen_cp0(ctx, op1, rt, rd);
break;
But looking into gen_cp0() in same file, there is no case
statement for OPC_DMFC0 and OPC_DMTC0. Looks to me that this
results in a RI exception.
Do I overlook anything here or is DMFC0/DMTC0 decoding
missing in gen_cp0()?
Dirk
next reply other threads:[~2007-01-10 20:32 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-01-10 20:32 Dirk Behme [this message]
2007-01-10 23:44 ` [Qemu-devel] Decode of MIPS DMFC0 and DMTC0 Thiemo Seufer
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