Re: [Qemu-devel] Preliminary Malta platform support

[Stefan Weil <Stefan.Weil@weilnetz.de>]

Aurelien Jarno schrieb:
> Aurelien Jarno a écrit :
>> Hi,
>>
>> I have recently worked on adding support for the Malta platform [1] with
>> a CoreLV CPU in QEMU. Due to lack of time this is currently not
>> finished, but if you want to try, my preliminary patches are now public.
>> It currently only works with a mipsel platform.
>>
>> They are available on http://temp.aurel32.net/ . The patches 1 to 4
>> correspond to the patches I have just posted. The patch 5 still needs
>> some work, patch 6 is almost ready. See the header of the patches for
>> more information.
>>

Hello Aurelien,

merci pour l'emulation de MIPS malta. C'est très jolie.

I added the MIPS display device which I already published
in an earlier mail, so now Thiemo can see LINUX ON MALTA
scrolling. Maybe the colors need some tuning (is green on
black correct?). My console patch (published on the list
some minutes ago) is also needed for correct display.

The display was tested with the Malta patches and MIPS kernel
http://temp.aurel32.net/vmlinux-2.6.18.5-mipsel like this:

./mipsel-softmmu/qemu-system-mipsel -M malta -kernel vmlinux-2.6.18.5-mipsel

Alt-Ctrl-4 or Alt-Ctrl-5 should show the Malta ASCII display.

Regards
Stefan


Index: vl.h
===================================================================
RCS file: /sources/qemu/qemu/vl.h,v
retrieving revision 1.170
diff -u -b -B -u -r1.170 vl.h
--- vl.h    10 Jan 2007 16:25:04 -0000    1.170
+++ vl.h    11 Jan 2007 19:33:10 -0000
@@ -302,6 +302,7 @@
     QEMUBH *bh;
 } CharDriverState;
 
+CharDriverState *qemu_chr_open(const char *filename);
 void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
 int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
 void qemu_chr_send_event(CharDriverState *s, int event);


--- hw/mips_malta.c    2007-01-11 20:34:59.000000000 +0100
+++ hw/mips_malta.c    2007-01-10 19:16:44.000000000 +0100
@@ -64,6 +64,26 @@
     }
 }
 
+/* MIPS ASCII display */
+#define ASCII_DISPLAY_POS_BASE 0x1f000418
+static char mips_display_text[8];
+static CharDriverState *mips_display;
+static void malta_display_writel(target_phys_addr_t addr, uint32_t val)
+{
+    if (mips_display == 0) {
+        mips_display = qemu_chr_open("vc");
+        qemu_chr_printf(mips_display, "\e[HMIPS Display\r\n");
+        qemu_chr_printf(mips_display, "+--------+\r\n");
+        qemu_chr_printf(mips_display, "+        +\r\n");
+        qemu_chr_printf(mips_display, "+--------+\r\n");
+    }
+    if (addr >= ASCII_DISPLAY_POS_BASE && addr < ASCII_DISPLAY_POS_BASE
+ 4 * 2 * 8) {
+        unsigned index = (addr - ASCII_DISPLAY_POS_BASE) / 4 / 2;
+        mips_display_text[index] = (char)val;
+        qemu_chr_printf(mips_display, "\e[H\n\n|\e[32m%-8.8s\e[00m|",
mips_display_text);
+    }
+}
+
 /* Malta FPGA */
 static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
 {
@@ -168,7 +188,7 @@
     break;
 
     /* ASCIIWORD, ASCIIPOS0 to ASCIIPOS7 Registers */
-    /* XXX: implement a 8-character ASCII display */
+    /* 8-character ASCII display */
     case 0x000410:
     case 0x000418:
     case 0x000420:
@@ -178,6 +198,7 @@
     case 0x000440:
     case 0x000448:
     case 0x000450:
+        malta_display_writel(addr, val);
     break;
 
     /* SOFTRES Register */