[Qemu-devel] Preliminary Malta platform support

[Qemu-devel] Preliminary Malta platform support

[Aurelien Jarno]

Hi,

I have recently worked on adding support for the Malta platform [1] with
a CoreLV CPU in QEMU. Due to lack of time this is currently not
finished, but if you want to try, my preliminary patches are now public.
It currently only works with a mipsel platform.

They are available on http://temp.aurel32.net/ . The patches 1 to 4 
correspond to the patches I have just posted. The patch 5 still needs
some work, patch 6 is almost ready. See the header of the patches for
more information.

Bye,
Aurelien

[1] http://www.linux-mips.org/wiki/Mips_Malta

-- 
  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   aurel32@debian.org         | aurelien@aurel32.net
   `-    people.debian.org/~aurel32 | www.aurel32.net

Re: [Qemu-devel] Preliminary Malta platform support

[Aurelien Jarno]

Aurelien Jarno a écrit :
> Hi,
> 
> I have recently worked on adding support for the Malta platform [1] with
> a CoreLV CPU in QEMU. Due to lack of time this is currently not
> finished, but if you want to try, my preliminary patches are now public.
> It currently only works with a mipsel platform.
> 
> They are available on http://temp.aurel32.net/ . The patches 1 to 4 
> correspond to the patches I have just posted. The patch 5 still needs
> some work, patch 6 is almost ready. See the header of the patches for
> more information.
> 

There was a bug in the PCI IRQ routing, which caused the network to not
work correctly. This is now fixed, the patches are at the same locations.

-- 
  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   aurel32@debian.org         | aurelien@aurel32.net
   `-    people.debian.org/~aurel32 | www.aurel32.net

Re: [Qemu-devel] Preliminary Malta platform support

[Stefan Weil]

Aurelien Jarno schrieb:
> Aurelien Jarno a écrit :
>> Hi,
>>
>> I have recently worked on adding support for the Malta platform [1] with
>> a CoreLV CPU in QEMU. Due to lack of time this is currently not
>> finished, but if you want to try, my preliminary patches are now public.
>> It currently only works with a mipsel platform.
>>
>> They are available on http://temp.aurel32.net/ . The patches 1 to 4
>> correspond to the patches I have just posted. The patch 5 still needs
>> some work, patch 6 is almost ready. See the header of the patches for
>> more information.
>>

Hello Aurelien,

merci pour l'emulation de MIPS malta. C'est très jolie.

I added the MIPS display device which I already published
in an earlier mail, so now Thiemo can see LINUX ON MALTA
scrolling. Maybe the colors need some tuning (is green on
black correct?). My console patch (published on the list
some minutes ago) is also needed for correct display.

The display was tested with the Malta patches and MIPS kernel
http://temp.aurel32.net/vmlinux-2.6.18.5-mipsel like this:

./mipsel-softmmu/qemu-system-mipsel -M malta -kernel vmlinux-2.6.18.5-mipsel

Alt-Ctrl-4 or Alt-Ctrl-5 should show the Malta ASCII display.

Regards
Stefan


Index: vl.h
===================================================================
RCS file: /sources/qemu/qemu/vl.h,v
retrieving revision 1.170
diff -u -b -B -u -r1.170 vl.h
--- vl.h    10 Jan 2007 16:25:04 -0000    1.170
+++ vl.h    11 Jan 2007 19:33:10 -0000
@@ -302,6 +302,7 @@
     QEMUBH *bh;
 } CharDriverState;
 
+CharDriverState *qemu_chr_open(const char *filename);
 void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
 int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
 void qemu_chr_send_event(CharDriverState *s, int event);


--- hw/mips_malta.c    2007-01-11 20:34:59.000000000 +0100
+++ hw/mips_malta.c    2007-01-10 19:16:44.000000000 +0100
@@ -64,6 +64,26 @@
     }
 }
 
+/* MIPS ASCII display */
+#define ASCII_DISPLAY_POS_BASE 0x1f000418
+static char mips_display_text[8];
+static CharDriverState *mips_display;
+static void malta_display_writel(target_phys_addr_t addr, uint32_t val)
+{
+    if (mips_display == 0) {
+        mips_display = qemu_chr_open("vc");
+        qemu_chr_printf(mips_display, "\e[HMIPS Display\r\n");
+        qemu_chr_printf(mips_display, "+--------+\r\n");
+        qemu_chr_printf(mips_display, "+        +\r\n");
+        qemu_chr_printf(mips_display, "+--------+\r\n");
+    }
+    if (addr >= ASCII_DISPLAY_POS_BASE && addr < ASCII_DISPLAY_POS_BASE
+ 4 * 2 * 8) {
+        unsigned index = (addr - ASCII_DISPLAY_POS_BASE) / 4 / 2;
+        mips_display_text[index] = (char)val;
+        qemu_chr_printf(mips_display, "\e[H\n\n|\e[32m%-8.8s\e[00m|",
mips_display_text);
+    }
+}
+
 /* Malta FPGA */
 static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
 {
@@ -168,7 +188,7 @@
     break;
 
     /* ASCIIWORD, ASCIIPOS0 to ASCIIPOS7 Registers */
-    /* XXX: implement a 8-character ASCII display */
+    /* 8-character ASCII display */
     case 0x000410:
     case 0x000418:
     case 0x000420:
@@ -178,6 +198,7 @@
     case 0x000440:
     case 0x000448:
     case 0x000450:
+        malta_display_writel(addr, val);
     break;
 
     /* SOFTRES Register */

Re: [Qemu-devel] Preliminary Malta platform support

[Aurelien Jarno]

On Thu, Jan 11, 2007 at 08:55:28PM +0100, Stefan Weil wrote:
> 
> Hello Aurelien,

Hi!

> merci pour l'emulation de MIPS malta. C'est très jolie.
> 
> I added the MIPS display device which I already published
> in an earlier mail, so now Thiemo can see LINUX ON MALTA
> scrolling. Maybe the colors need some tuning (is green on
> black correct?). My console patch (published on the list
> some minutes ago) is also needed for correct display.
> 
> The display was tested with the Malta patches and MIPS kernel
> http://temp.aurel32.net/vmlinux-2.6.18.5-mipsel like this:
> 
> ./mipsel-softmmu/qemu-system-mipsel -M malta -kernel vmlinux-2.6.18.5-mipsel
> 
> Alt-Ctrl-4 or Alt-Ctrl-5 should show the Malta ASCII display.
> 

Thanks for your work. I have just tested it, it works well. I will
include it in the next version of my patches. I would be nice if your
console patch could be merged meanwhile.

About the color I don't know as I don't own such a board. I guess Thiemo
knows the answer.

Tschüss,
AUrelien

-- 
  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   aurel32@debian.org         | aurelien@aurel32.net
   `-    people.debian.org/~aurel32 | www.aurel32.net

Re: [Qemu-devel] Preliminary Malta platform support

[Alexander Voropay]

"Stefan Weil" <Stefan.Weil@weilnetz.de> wrote:

>I added the MIPS display device which I already published
>in an earlier mail, so now Thiemo can see LINUX ON MALTA
>scrolling.

 Linux kernel is scrolling this message *endless* and will waste a
console output. Most of MIPS Malta emulators implement
this device "Malta Display" in the separate small window.
Look for example on the screenshot from the Virtutech Simics
running MIPS Malta Linux:
http://www.nwpi.ru/~alec/mips/simics-malta.jpg


--
-=AV=-

Re: [Qemu-devel] Preliminary Malta platform support

[Aurelien Jarno]

Alexander Voropay a écrit :
> "Stefan Weil" <Stefan.Weil@weilnetz.de> wrote:
> 
>> I added the MIPS display device which I already published
>> in an earlier mail, so now Thiemo can see LINUX ON MALTA
>> scrolling.
> 
>  Linux kernel is scrolling this message *endless* and will waste a
> console output. Most of MIPS Malta emulators implement
> this device "Malta Display" in the separate small window.
> Look for example on the screenshot from the Virtutech Simics
> running MIPS Malta Linux:
> http://www.nwpi.ru/~alec/mips/simics-malta.jpg

I don't see the problem here. You can have a lot of virtual console in
QEMU. The Malta platform currently emulates a parallel port and two
serial ports, so the malta display is in the fourth position. Even with
a video card and the third serial port emulated, that will put it in
sixth position, which is IHMO reasonnable.

-- 
  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   aurel32@debian.org         | aurelien@aurel32.net
   `-    people.debian.org/~aurel32 | www.aurel32.net

Re: [Qemu-devel] Preliminary Malta platform support

[Aurelien Jarno]

Aurelien Jarno a écrit :
> On Thu, Jan 11, 2007 at 08:55:28PM +0100, Stefan Weil wrote:
>> Hello Aurelien,
> 
> Hi!
> 
>> merci pour l'emulation de MIPS malta. C'est très jolie.
>>
>> I added the MIPS display device which I already published
>> in an earlier mail, so now Thiemo can see LINUX ON MALTA
>> scrolling. Maybe the colors need some tuning (is green on
>> black correct?). My console patch (published on the list
>> some minutes ago) is also needed for correct display.
>>
>> The display was tested with the Malta patches and MIPS kernel
>> http://temp.aurel32.net/vmlinux-2.6.18.5-mipsel like this:
>>
>> ./mipsel-softmmu/qemu-system-mipsel -M malta -kernel vmlinux-2.6.18.5-mipsel
>>
>> Alt-Ctrl-4 or Alt-Ctrl-5 should show the Malta ASCII display.
>>
> 
> Thanks for your work. I have just tested it, it works well. I will
> include it in the next version of my patches. I would be nice if your
> console patch could be merged meanwhile.
> 

I have update my patchset, with your code merged. I have also added a
display of the LED bar in the same console.

As usual, you can fetch it from http://temp.aurel32.net

-- 
  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   aurel32@debian.org         | aurelien@aurel32.net
   `-    people.debian.org/~aurel32 | www.aurel32.net

Re: [Qemu-devel] Preliminary Malta platform support

[Thiemo Seufer]

Stefan Weil wrote:
> Aurelien Jarno schrieb:
> > Aurelien Jarno a écrit :
> >> Hi,
> >>
> >> I have recently worked on adding support for the Malta platform [1] with
> >> a CoreLV CPU in QEMU. Due to lack of time this is currently not
> >> finished, but if you want to try, my preliminary patches are now public.
> >> It currently only works with a mipsel platform.
> >>
> >> They are available on http://temp.aurel32.net/ . The patches 1 to 4
> >> correspond to the patches I have just posted. The patch 5 still needs
> >> some work, patch 6 is almost ready. See the header of the patches for
> >> more information.
> >>
> 
> Hello Aurelien,
> 
> merci pour l'emulation de MIPS malta. C'est très jolie.
> 
> I added the MIPS display device which I already published
> in an earlier mail, so now Thiemo can see LINUX ON MALTA
> scrolling. Maybe the colors need some tuning (is green on
> black correct?).

The hardware displays red on black, but that's a very minor issue. :-)


Thiemo

Re: [Qemu-devel] Preliminary Malta platform support

[Stefan Weil]

[-- Attachment #1: Type: text/plain, Size: 1346 bytes --]

Hi,

with this patch the latest QEMU from CVS will run a REDBOOT firmware.

* The patch includes Aurelien Jarno's latest change for gt64xxx.c.
* It adds an new EEPROM 24C01 / 24C02 emulation needed for SDRAM SPD
  (still incomplete but sufficient for REDBOOT).
* It also permits to load firmware images smaller than the maximum
  BIOS size (code copied from mips_r4k.c).

My REDBOOT firmware image for Malta (little endian) can be downloaded here:
http://svn.berlios.de/wsvn/ar7-firmware/qemu/trunk/pc-bios/mips_bios.bin?op=file&rev=0&sc=0

Stefan

Boot log:

$ mipsel-softmmu/qemu-system-mipsel -M malta -L pc-bios /dev/zero
-nographic 2>/dev/null
(qemu) +
FLASH: driver init failed: Driver does not support device
IDE failed to identify unit 0 - wrote: a0, read: 20
IDE failed to identify unit 0 - wrote: b0, read: 30
Sorry, FLASH config exceeds available space in FIS directory
Ethernet eth0: MAC address 00:00:00:00:00:00
No IP info for device!

RedBoot(tm) bootstrap and debug environment [ROM]
Non-certified release, version UNKNOWN - built 11:35:22, Dec 27 2006

Platform: Malta (MIPS32 4Kc)
Copyright (C) 2000, 2001, 2002, 2003, 2004 Red Hat, Inc.
Copyright (C) 2003, 2004, 2005, 2006 eCosCentric Limited

RAM: 0x80000400-0x82000000, [0x8000cc80-0x81ef1000] available
FLASH: 0x00000000 - 0x1, 0 blocks of 0x00000000 bytes each.
RedBoot>


[-- Attachment #2: malta.patch --]
[-- Type: text/plain, Size: 8446 bytes --]

Index: hw/mips_malta.c
===================================================================
--- hw/mips_malta.c	(Revision 421)
+++ hw/mips_malta.c	(Arbeitskopie)
@@ -45,6 +45,7 @@
     uint32_t leds;
     uint32_t brk;
     uint32_t gpout;
+    uint32_t i2cin;
     uint32_t i2coe;
     uint32_t i2cout;
     uint32_t i2csel;
@@ -85,6 +86,122 @@
     qemu_chr_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text);
 }
 
+/*
+ * EEPROM 24C01 / 24C02 emulation.
+ *
+ * Emulation for serial EEPROMs:
+ * 24C01 - 1024 bit (128 x 8)
+ * 24C02 - 2048 bit (256 x 8)
+ *
+ * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
+ */
+
+//~ #define DEBUG
+
+#if defined(DEBUG)
+#  define logout(fmt, args...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ##args)
+#else
+#  define logout(fmt, args...) ((void)0)
+#endif
+
+struct _eeprom24c0x_t {
+  uint8_t tick;
+  uint8_t address;
+  uint8_t command;
+  uint8_t ack;
+  uint8_t scl;
+  uint8_t sda;
+  uint16_t size;
+  uint8_t data;
+  uint8_t contents[256];
+};
+
+typedef struct _eeprom24c0x_t eeprom24c0x_t;
+
+static eeprom24c0x_t eeprom = {
+    //~ # Determine Size in Mbit
+    //~ #     SIZE = SDRAM_WIDTH * NUM_DEVICE_BANKS * 2 ^ (NUM_ROW_BITS + NUM_COL_BITS)
+    //~ 4 * 2 * 2 ^ 8
+    contents: {
+        /* 00000000: */ 0x80,0x08,0x04,0x0D,0x0A,0x01,0x40,0x00,0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
+        //~ /* 00000010: */ 0x8F,0x04,0x04,0x01,0x01,0x00,0x0E,0x00,0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0x40,
+        /* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x0E,0x00,0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0x40,
+        /* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+        /* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0,
+        /* 00000040: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+        /* 00000050: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+        /* 00000060: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+        /* 00000070: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4,
+    },
+};
+
+static uint8_t eeprom24c0x_read()
+{
+    logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
+        eeprom.tick, eeprom.scl, eeprom.sda, eeprom.data);
+    return eeprom.sda;
+}
+
+static void eeprom24c0x_write(int scl, int sda)
+{
+    //~ uint8_t scl = eeprom.scl;
+    //~ uint8_t sda = eeprom.sda;
+    if (eeprom.scl && scl && (eeprom.sda != sda)) {
+        logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
+                eeprom.tick, eeprom.scl, scl, eeprom.sda, sda, sda ? "stop" : "start");
+        if (!sda) {
+            eeprom.tick = 1;
+            eeprom.command = 0;
+        }
+    } else if (eeprom.tick == 0 && !eeprom.ack) {
+        /* Waiting for start. */
+        logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
+                eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
+    } else if (!eeprom.scl && scl) {
+        logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
+                eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
+        if (eeprom.ack) {
+            logout("\ti2c ack bit = 0\n");
+            sda = 0;
+            eeprom.ack = 0;
+        } else if (eeprom.sda == sda) {
+            uint8_t bit = (sda != 0);
+            logout("\ti2c bit = %d\n", bit);
+            if (eeprom.tick < 9) {
+                eeprom.command <<= 1;
+                eeprom.command += bit;
+                eeprom.tick++;
+                if (eeprom.tick == 9) {
+                    logout("\tcommand 0x%04x, %s\n", eeprom.command, bit ? "read" : "write");
+                    eeprom.ack = 1;
+                }
+            } else if (eeprom.tick < 17) {
+                if (eeprom.command & 1) {
+                    sda = ((eeprom.data & 0x80) != 0);
+                }
+                eeprom.address <<= 1;
+                eeprom.address += bit;
+                eeprom.tick++;
+                eeprom.data <<= 1;
+                if (eeprom.tick == 17) {
+                    eeprom.data = eeprom.contents[eeprom.address];
+                    logout("\taddress 0x%04x, data 0x%02x\n", eeprom.address, eeprom.data);
+                    eeprom.ack = 1;
+                    eeprom.tick = 0;
+                }
+            } else if (eeprom.tick >= 17) {
+                sda = 0;
+            }
+        } else {
+            logout("\tsda changed with raising scl\n");
+        }
+    } else {
+        logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
+    }
+    eeprom.scl = scl;
+    eeprom.sda = sda;
+}
+
 static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
 {
     MaltaFPGAState *s = opaque;
@@ -142,7 +259,7 @@
 
     /* I2CINP Register */
     case 0x00b00:
-        val = 0x00000003;
+        val = ((s->i2cin & ~1) | eeprom24c0x_read());
         break;
 
     /* I2COE Register */
@@ -235,7 +352,8 @@
 
     /* I2COUT Register */
     case 0x00b10:
-        s->i2cout = val & 0x03;
+        eeprom24c0x_write(val & 0x02, val & 0x01);
+        s->i2cout = val;
         break;
 
     /* I2CSEL Register */
@@ -497,13 +615,13 @@
 {
     char buf[1024];
     unsigned long bios_offset;
+    int bios_size;
     int64_t kernel_addr;
     PCIBus *pci_bus;
     CPUState *env;
     RTCState *rtc_state;
     /* fdctrl_t *floppy_controller; */
     MaltaFPGAState *malta_fpga;
-    int ret;
 
     env = cpu_init();
     register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
@@ -512,12 +630,25 @@
     /* allocate RAM */
     cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
 
+    /* Try to load a BIOS image. If this fails, we continue regardless,
+       but initialize the hardware ourselves. When a kernel gets
+       preloaded we also initialize the hardware, since the BIOS wasn't
+       run. */
+    bios_offset = ram_size + vga_ram_size;
     /* Map the bios at two physical locations, as on the real board */
-    bios_offset = ram_size + vga_ram_size;
     cpu_register_physical_memory(0x1e000000LL,
                                  BIOS_SIZE, bios_offset | IO_MEM_ROM);
     cpu_register_physical_memory(0x1fc00000LL,
                                  BIOS_SIZE, bios_offset | IO_MEM_ROM);
+    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
+    bios_size = load_image(buf, phys_ram_base + bios_offset);
+    if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
+        fprintf(stderr, "qemu: MIPS bios '%s' loaded, %d bytes\n",
+                buf, bios_size);
+    } else {
+        fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
+                buf);
+    }
 
     /* Load a BIOS image except if a kernel image has been specified. In
        the later case, just write a small bootloader to the flash
@@ -529,14 +660,6 @@
         env->initrd_filename = initrd_filename;
         kernel_addr = load_kernel(env);
         write_bootloader(env, bios_offset, kernel_addr);
-    } else {
-        snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
-        ret = load_image(buf, phys_ram_base + bios_offset);
-        if (ret != BIOS_SIZE) {
-            fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
-                    buf);
-            exit(1);
-        }
     }
 
     /* Board ID = 0x420 (Malta Board with CoreLV)
@@ -581,6 +704,9 @@
 
     /* Network card */
     network_init(pci_bus);
+
+    /* Select 1st serial console as default (because we don't have VGA). */
+    console_select(1);
 }
 
 QEMUMachine mips_malta_machine = {
Index: hw/gt64xxx.c
===================================================================
--- hw/gt64xxx.c	(Revision 421)
+++ hw/gt64xxx.c	(Arbeitskopie)
@@ -229,9 +229,12 @@
     target_phys_addr_t start, length;		   
 
     /* Update IO mapping */
-    start = s->regs[GT_PCI0IOLD] << 21;
-    length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
-    isa_mmio_init(start, length);
+    if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
+    {
+      start = s->regs[GT_PCI0IOLD] << 21;
+      length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
+      isa_mmio_init(start, length);
+    }
 }
 
 static void gt64120_writel (void *opaque, target_phys_addr_t addr,

Re: [Qemu-devel][PATCH] Preliminary Malta platform support

[Stefan Weil]

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Hi,

here is the patch which adds the EEPROM 24C01 / 24C02 emulation
needed for Redboot with MIPS Malta. It's now based on current
CVS HEAD. For those who want to try the Redboot image or
add it to CVS :-), please use the link given below.

Stefan


Stefan Weil schrieb:
> Hi,
>
> with this patch the latest QEMU from CVS will run a REDBOOT firmware.
>
> * The patch includes Aurelien Jarno's latest change for gt64xxx.c.
> * It adds an new EEPROM 24C01 / 24C02 emulation needed for SDRAM SPD
> (still incomplete but sufficient for REDBOOT).
> * It also permits to load firmware images smaller than the maximum
> BIOS size (code copied from mips_r4k.c).
>
> My REDBOOT firmware image for Malta (little endian) can be downloaded
> here:
> http://svn.berlios.de/wsvn/ar7-firmware/qemu/trunk/pc-bios/mips_bios.bin?op=file&rev=0&sc=0
>
> Stefan
>
> Boot log:
>
> $ mipsel-softmmu/qemu-system-mipsel -M malta -L pc-bios /dev/zero
> -nographic 2>/dev/null
> (qemu) +
> FLASH: driver init failed: Driver does not support device
> IDE failed to identify unit 0 - wrote: a0, read: 20
> IDE failed to identify unit 0 - wrote: b0, read: 30
> Sorry, FLASH config exceeds available space in FIS directory
> Ethernet eth0: MAC address 00:00:00:00:00:00
> No IP info for device!
>
> RedBoot(tm) bootstrap and debug environment [ROM]
> Non-certified release, version UNKNOWN - built 11:35:22, Dec 27 2006
>
> Platform: Malta (MIPS32 4Kc)
> Copyright (C) 2000, 2001, 2002, 2003, 2004 Red Hat, Inc.
> Copyright (C) 2003, 2004, 2005, 2006 eCosCentric Limited
>
> RAM: 0x80000400-0x82000000, [0x8000cc80-0x81ef1000] available
> FLASH: 0x00000000 - 0x1, 0 blocks of 0x00000000 bytes each.
> RedBoot>

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Index: hw/mips_malta.c
===================================================================
RCS file: /sources/qemu/qemu/hw/mips_malta.c,v
retrieving revision 1.12
diff -u -b -B -u -r1.12 mips_malta.c
--- hw/mips_malta.c	21 Feb 2007 22:43:42 -0000	1.12
+++ hw/mips_malta.c	22 Feb 2007 19:06:34 -0000
@@ -49,6 +49,7 @@
     uint32_t leds;
     uint32_t brk;
     uint32_t gpout;
+    uint32_t i2cin;
     uint32_t i2coe;
     uint32_t i2cout;
     uint32_t i2csel;
@@ -83,6 +84,124 @@
     qemu_chr_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text);
 }
 
+/*
+ * EEPROM 24C01 / 24C02 emulation.
+ *
+ * Emulation for serial EEPROMs:
+ * 24C01 - 1024 bit (128 x 8)
+ * 24C02 - 2048 bit (256 x 8)
+ *
+ * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
+ */
+
+//~ #define DEBUG
+
+#if defined(DEBUG)
+#  define logout(fmt, args...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ##args)
+#else
+#  define logout(fmt, args...) ((void)0)
+#endif
+
+struct _eeprom24c0x_t {
+  uint8_t tick;
+  uint8_t address;
+  uint8_t command;
+  uint8_t ack;
+  uint8_t scl;
+  uint8_t sda;
+  uint8_t data;
+  //~ uint16_t size;
+  uint8_t contents[256];
+};
+
+typedef struct _eeprom24c0x_t eeprom24c0x_t;
+
+static eeprom24c0x_t eeprom = {
+    contents: {
+        /* 00000000: */ 0x80,0x08,0x04,0x0D,0x0A,0x01,0x40,0x00,
+        /* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
+        /* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x0E,0x00,
+        /* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0x40,
+        /* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00,
+        /* 00000028: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+        /* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+        /* 00000038: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0,
+        /* 00000040: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+        /* 00000048: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+        /* 00000050: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+        /* 00000058: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+        /* 00000060: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+        /* 00000068: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+        /* 00000070: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+        /* 00000078: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4,
+    },
+};
+
+static uint8_t eeprom24c0x_read()
+{
+    logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
+        eeprom.tick, eeprom.scl, eeprom.sda, eeprom.data);
+    return eeprom.sda;
+}
+
+static void eeprom24c0x_write(int scl, int sda)
+{
+    if (eeprom.scl && scl && (eeprom.sda != sda)) {
+        logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
+                eeprom.tick, eeprom.scl, scl, eeprom.sda, sda, sda ? "stop" : "start");
+        if (!sda) {
+            eeprom.tick = 1;
+            eeprom.command = 0;
+        }
+    } else if (eeprom.tick == 0 && !eeprom.ack) {
+        /* Waiting for start. */
+        logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
+                eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
+    } else if (!eeprom.scl && scl) {
+        logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
+                eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
+        if (eeprom.ack) {
+            logout("\ti2c ack bit = 0\n");
+            sda = 0;
+            eeprom.ack = 0;
+        } else if (eeprom.sda == sda) {
+            uint8_t bit = (sda != 0);
+            logout("\ti2c bit = %d\n", bit);
+            if (eeprom.tick < 9) {
+                eeprom.command <<= 1;
+                eeprom.command += bit;
+                eeprom.tick++;
+                if (eeprom.tick == 9) {
+                    logout("\tcommand 0x%04x, %s\n", eeprom.command, bit ? "read" : "write");
+                    eeprom.ack = 1;
+                }
+            } else if (eeprom.tick < 17) {
+                if (eeprom.command & 1) {
+                    sda = ((eeprom.data & 0x80) != 0);
+                }
+                eeprom.address <<= 1;
+                eeprom.address += bit;
+                eeprom.tick++;
+                eeprom.data <<= 1;
+                if (eeprom.tick == 17) {
+                    eeprom.data = eeprom.contents[eeprom.address];
+                    logout("\taddress 0x%04x, data 0x%02x\n", eeprom.address, eeprom.data);
+                    eeprom.ack = 1;
+                    eeprom.tick = 0;
+                }
+            } else if (eeprom.tick >= 17) {
+                sda = 0;
+            }
+        } else {
+            logout("\tsda changed with raising scl\n");
+        }
+    } else {
+        logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom.tick, eeprom.scl, scl, eeprom.sda, sda);
+    }
+    eeprom.scl = scl;
+    eeprom.sda = sda;
+}
+
 static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
 {
     MaltaFPGAState *s = opaque;
@@ -140,7 +259,7 @@
 
     /* I2CINP Register */
     case 0x00b00:
-        val = 0x00000003;
+        val = ((s->i2cin & ~1) | eeprom24c0x_read());
         break;
 
     /* I2COE Register */
@@ -155,7 +274,7 @@
 
     /* I2CSEL Register */
     case 0x00b18:
-        val = s->i2cout;
+        val = s->i2csel;
         break;
 
     default:
@@ -234,12 +353,13 @@
 
     /* I2COUT Register */
     case 0x00b10:
-        s->i2cout = val & 0x03;
+        eeprom24c0x_write(val & 0x02, val & 0x01);
+        s->i2cout = val;
         break;
 
     /* I2CSEL Register */
     case 0x00b18:
-        s->i2cout = val & 0x01;
+        s->i2csel = val & 0x01;
         break;
 
     default:
@@ -270,6 +390,7 @@
     s->leds   = 0x00;
     s->brk    = 0x0a;
     s->gpout  = 0x00;
+    s->i2cin  = 0x3;
     s->i2coe  = 0x0;
     s->i2cout = 0x3;
     s->i2csel = 0x1;