Re: [Qemu-devel] [Bug] MIPS code fails at branch instruction

[Stefan Weil <Stefan.Weil@weilnetz.de>]

Thiemo Seufer wrote
> Stefan Weil wrote:
>> So an emulation has several options:
>>
>> 1. Show undefined behaviour (this is what it does today).
>> 2. Emulate the behaviour of existing CPUs as far as possible.
>> As different CPUs behave different, this must depend on the
>> current CPU.
>> 3. Display an error message.
> (3) is bad, as it amounts to a DoS.
DoS = Denial of Service? Then (1) is some kind of DoS, because QEMU hangs
with code which works on real hardware. I don't understand why an
error message (something printed to stdout or stderr like other boot
messages of QEMU) amounts to a DoS.
>> The current solution (1) is not good, because users get crashes
>> and don't know the reason, and experienced users spend a lot of
>> time with debugging (at least I did).
>>
>> Solution (2) is needed to run existing binary code.
>>
>> Solution (3) is the minimum I expect of an emulation like QEMU.
>>
>> I prefer a mix of solutions (2) and (3): display a message and
>> try to emulate the original behaviour.
>>
>> Do you agree, and would you accept patches which implement this?
> If the AR7 CPU spec defines the semantics of branch delay slots more
> precisely than the architecture spec then I'll consider a patch.
AR7 claims to use a 4KEc CPU, so there is only the official
spec from MIPS.
> If this isn't the case then I ask you to use a non-broken compiler/
> assembly code.
What about closed source binary code (firmware in my case)?
Of course it can be patched, but this is more work than implementing
(2) and (3) in QEMU.

Stefan