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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Thomas Huth <thuth@redhat.com>
Cc: qemu-devel@nongnu.org, "Michael Tsirkin" <mst@redhat.com>,
	"Ben Widawsky" <bwidawsk@kernel.org>,
	linux-cxl@vger.kernel.org, linuxarm@huawei.com,
	"Ira Weiny" <ira.weiny@intel.com>,
	"Markus Armbruster" <armbru@redhat.com>,
	"Gregory Price" <gourry.memverge@gmail.com>,
	"Mike Maslenkin" <mike.maslenkin@gmail.com>,
	"Dave Jiang" <dave.jiang@intel.com>,
	"Marc-André Lureau" <marcandre.lureau@redhat.com>
Subject: Re: [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
Date: Fri, 24 Feb 2023 20:02:59 +0100	[thread overview]
Message-ID: <45b86050-0f0b-d222-c32f-9d6f23246574@linaro.org> (raw)
In-Reply-To: <20230223142748.0000662f@huawei.com>

On 23/2/23 15:27, Jonathan Cameron wrote:
> On Thu, 23 Feb 2023 08:37:46 +0100
> Markus Armbruster <armbru@redhat.com> wrote:
> 
>> Thomas Huth <thuth@redhat.com> writes:
>>
>>> On 22/02/2023 19.16, Philippe Mathieu-Daudé wrote:
>>>> +Thomas (meson) & Marc-André (conditional QAPI)
>>>
>>> + Markus
>>>   
>>>> On 22/2/23 17:49, Jonathan Cameron wrote:
>>
>> [...]
>>
>>>>>>>> Doesn't these need
>>>>>>>>
>>>>>>>>          'if': 'CONFIG_CXL_MEM_DEVICE',
>>>>>>>>
>>>>>>>> ?
>>>>>>>
>>>>>>> If I make this change I get a bunch of
>>>>>>>
>>>>>>> ./qapi/qapi-types-cxl.h:18:13: error: attempt to use poisoned "CONFIG_CXL_MEM_DEVICE"
>>>>>>>       18 | #if defined(CONFIG_CXL_MEM_DEVICE)
>>>>>>
>>>>>> Err, I meant the generic CONFIG_CXL, not CONFIG_CXL_MEM_DEVICE.
>>>>>>   
>>>>>>> It's a target specific define (I think) as built alongside PCI_EXPRESS
>>>>>>> Only CXL_ACPI is specifically included by x86 and arm64 (out of tree)
>>>>>>>
>>>>>>> To be honest though I don't fully understand the QEMU build system so the reason
>>>>>>> for the error might be wrong.
>>>>>>
>>>>>> You need to restrict to system emulation (the 'have_system' check):
>>>>>
>>>>> This doesn't help - still have
>>>>> attempt to used poisoned "CONFIG_CXL"
>>>
>>> Not sure how the QAPI generator works, but target specific config switches can only be used in target specific json files there, so that's machine-target.json and misc-target.json currently, as far as I know. Not sure how the QAPI generator distinguishes between common and target specific code, though ... just by the "-target" suffix? Maybe Markus or Marc-André can comment on that.
>>
>> Whenever you use a poisoned macro in a conditional, all the code
>> generated for this .json file (we call it a "QAPI schema module")
>> becomes target-dependent.  The QAPI code generator itself is blissfully
>> unaware of this.
>>
>> Since target-dependent code needs to be compiled differently, the build
>> process needs to be know which modules are target-dependent.  We do this
>> in one of the stupidest ways that could possibly work: a module is
>> target-dependent if its name ends with "-target".  There are just two
>> right now: qapi/machine-target.json and qapi/misc-target.json.
>>
>> The logic resides in qapi/meson.build.  Look for
>>
>>      if module.endswith('-target')
> 
> Thanks for all the pointers.
>>
>> Questions?
> 
> Is it sensible to make the cxl stuff all target dependent and do the following?
> I like that we can get rid of the stubs if we do this but I'm sure there are
> disadvantages. Only alternative I can currently see is continue to have
> stubs and not make the qmp commands conditional on them doing anything useful.

I still don't understand what is the target-dependent part of CXL.

IIUC CXL depends on PCIe which isn't target dependent.


  parent reply	other threads:[~2023-02-24 19:03 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-21 15:21 [PATCH v5 0/8] hw/cxl: RAS error emulation and injection Jonathan Cameron via
2023-02-21 15:21 ` [PATCH v5 1/8] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register Jonathan Cameron via
2023-02-21 15:21 ` [PATCH v5 2/8] hw/pci/aer: Add missing routing for AER errors Jonathan Cameron via
2023-02-21 15:21 ` [PATCH v5 3/8] hw/pci-bridge/cxl_root_port: Wire up AER Jonathan Cameron via
2023-02-21 15:21 ` [PATCH v5 4/8] hw/pci-bridge/cxl_root_port: Wire up MSI Jonathan Cameron via
2023-02-21 15:21 ` [PATCH v5 5/8] hw/mem/cxl-type3: Add AER extended capability Jonathan Cameron via
2023-02-21 15:21 ` [PATCH v5 6/8] hw/cxl: Fix endian issues in CXL RAS capability defaults / masks Jonathan Cameron via
2023-02-21 22:06   ` Philippe Mathieu-Daudé
2023-02-21 15:21 ` [PATCH v5 7/8] hw/pci/aer: Make PCIE AER error injection facility available for other emulation to use Jonathan Cameron via
2023-02-21 22:08   ` Philippe Mathieu-Daudé
2023-02-21 15:21 ` [PATCH v5 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support Jonathan Cameron via
2023-02-21 15:48   ` Dave Jiang
2023-02-21 22:15   ` Philippe Mathieu-Daudé
2023-02-22 14:53     ` Jonathan Cameron via
2023-02-22 15:32       ` Philippe Mathieu-Daudé
2023-02-22 16:49         ` Jonathan Cameron via
2023-02-22 18:16           ` Philippe Mathieu-Daudé
2023-02-23  6:58             ` Thomas Huth
2023-02-23  7:37               ` Markus Armbruster
2023-02-23 14:27                 ` Jonathan Cameron via
2023-02-24 17:37                   ` Jonathan Cameron via
2023-02-24 19:02                   ` Philippe Mathieu-Daudé [this message]
2023-02-27  9:40                     ` Markus Armbruster
2023-02-22 18:28       ` Markus Armbruster
2023-10-27  4:54   ` Markus Armbruster
2023-10-31 17:55     ` Jonathan Cameron via
2023-10-31 17:55       ` Jonathan Cameron
2023-11-02  6:47       ` Markus Armbruster

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