From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1HWwxU-0007jU-Oo for qemu-devel@nongnu.org; Thu, 29 Mar 2007 11:54:40 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1HWwxT-0007jA-4w for qemu-devel@nongnu.org; Thu, 29 Mar 2007 11:54:40 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1HWwxT-0007j7-2H for qemu-devel@nongnu.org; Thu, 29 Mar 2007 10:54:39 -0500 Received: from an-out-0708.google.com ([209.85.132.243]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1HWwur-00020o-L5 for qemu-devel@nongnu.org; Thu, 29 Mar 2007 11:51:57 -0400 Received: by an-out-0708.google.com with SMTP id d40so412664and for ; Thu, 29 Mar 2007 08:51:57 -0700 (PDT) Message-ID: <460BE098.6010109@codemonkey.ws> Date: Thu, 29 Mar 2007 10:51:52 -0500 From: Anthony Liguori MIME-Version: 1.0 Subject: Re: [Qemu-devel] [RFC/experimental patch] qemu (x86_64 on x86_64 -no-kqemu) compiles with gcc4 and works References: <200703241850.03116.axel.zeuner@gmx.de> <200703260816.00508.axel.zeuner@gmx.de> <460B1F65.6040308@codemonkey.ws> <200703290803.14629.axel.zeuner@gmx.de> In-Reply-To: <200703290803.14629.axel.zeuner@gmx.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Axel Zeuner Cc: qemu-devel@nongnu.org Axel Zeuner wrote: > Hi Anthony, > > On Thursday 29 March 2007 04:07, you wrote: > >> Axel Zeuner wrote: >> >>> Hi Anthony, >>> >>> On Monday 26 March 2007 01:44, you wrote: >>> >>>> Axel Zeuner wrote: >>>> >>>>> On Saturday 24 March 2007 21:15, Anthony Liguori wrote: >>>>> >>>>>> The tricky thing I still can't figure out is how to get ASM_SOFTMMU >>>>>> working. The problem is GLUE(st, SUFFIX) function. First GCC cannot >>>>>> deal with the register pressure. The problem I can't seem to fix >>>>>> though is that GCC sticks %1 in %esi because we're only using an "r" >>>>>> constraint, not a "q" constraint. This results in the generation of >>>>>> %sib which is an invalid register. However, refactoring the code to >>>>>> not require a "q" constraint doesn't seem to help either. >>>>>> >>>>> Hi Anthony, >>>>> could you please try the attached patch for softmmu_header.h? Allows >>>>> compiling with gcc4 and ASM_SOFTMMU. >>>>> >>>> That did the trick. Could you explain what your changes did? >>>> >>> QEMU/i386 has only 3 three available registers if TARGET_I386 is selected >>> because ebx,ebp,esi,edi are used by the environment and T0, T1, T3( AKA >>> A0). This makes inline assembly really ugly. The called external C >>> functions in ASM_SOFTMMU are REGPARM(1,2), i.e. require their first >>> arguments in eax, edx. >>> >> Based on some feedback from Paul Brook, I wrote another patch that just >> disables the use of register variables for GCC4. I think this is a >> considerably less hackish way to go about this. >> >> The generated code won't be as nice of course but at least it works. >> The patch applies against your cvtasm patches. >> > Looks good to me, sorry I had no time yet to test your patch. Did you check > the performance impact of your changes? > Perhaps it is possible to use register variables in dependence of the register > count of the host processor. > Yes, I need to update the patch to include a && defined(__i386__) and also to add the proper guards to the other architectures. Regards, Anthony Liguori > Kind Regards > Axel > >