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Thu, 07 Dec 2023 05:19:14 -0800 (PST) Message-ID: <461b2494-cc2e-4d0e-bcc0-8dcf93389eb4@linaro.org> Date: Thu, 7 Dec 2023 14:19:13 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/arm: Restrict ARM_FEATURE_PMU to system emulation Content-Language: en-US To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell References: <20231207111048.50568-1-philmd@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20231207111048.50568-1-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/12/23 12:10, Philippe Mathieu-Daudé wrote: > ARM Performance Monitor Unit is not reachable from user > emulation, restrict it to system emulation. > > Signed-off-by: Philippe Mathieu-Daudé > --- > target/arm/cpu.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 51f57fd5b4..60cf747fd6 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1410,6 +1410,7 @@ static Property arm_cpu_pmsav7_dregion_property = > pmsav7_dregion, > qdev_prop_uint32, uint32_t); > > +#ifndef CONFIG_USER_ONLY > static bool arm_get_pmu(Object *obj, Error **errp) > { > ARMCPU *cpu = ARM_CPU(obj); > @@ -1432,6 +1433,7 @@ static void arm_set_pmu(Object *obj, bool value, Error **errp) > } > cpu->has_pmu = value; > } > +#endif > > unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) > { > @@ -1592,12 +1594,12 @@ void arm_cpu_post_init(Object *obj) > if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { > qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); > } > -#endif > > if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { > cpu->has_pmu = true; > object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu); > } > +#endif I think this patch is incomplete: should the PMU registers in v7_cp_reginfo[] be restricted to TCG?