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Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH 20/37] target/i386: reimplement 0x0f 0x60-0x6f, add AVX Content-Language: en-US To: Paolo Bonzini Cc: qemu-devel@nongnu.org References: <20220911230418.340941-1-pbonzini@redhat.com> <20220911230418.340941-21-pbonzini@redhat.com> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2001:4860:4864:20::36; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x36.google.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.628, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/13/22 11:56, Paolo Bonzini wrote: > On Mon, Sep 12, 2022 at 1:41 PM Richard Henderson > wrote: >> >> On 9/12/22 00:04, Paolo Bonzini wrote: >>> +/* >>> + * 00 = p* Pq, Qq (if mmx not NULL; no VEX) >>> + * 66 = vp* Vx, Hx, Wx >>> + * >>> + * These are really the same encoding, because 1) V is the same as P when VEX.V >>> + * is not present 2) P and Q are the same as H and W apart from MM/XMM >>> + */ >>> +static inline void gen_binary_int_sse(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode, >>> + SSEFunc_0_eppp mmx, SSEFunc_0_eppp xmm, SSEFunc_0_eppp ymm) >> >> No need to inline. > > Yes and no, the compiler should indeed be able to figure it out, but > both the assert() and the calls are meant to be optimized out by > inlining. So this kind of function would be even an always_inline > candidate. Yes, I get that, I just prefer by default to allow the compiler to figure it out. Obviously there are parts of the code base where we use always_inline and more, but this part is never going to be performance critical. Over-use of inline generally leads to Werror from clang, for the unused function case. > I'm not sure about that, because there are quite a few cases handled > by more complex gen_* functions, which are helper-based (so not simple > calls to gvec functions where you have maxsz/oprsz) and are not > handled by the common gen_*_sse. For example gen_CVTPI2Px, > gen_MASKMOV, gen_PSRLDQ_i, gen_SSE4a_I, gen_VCVTSI2Sx, ... All of > these would have to add extra code to set the pointers and to clear > the high ymm bits. Fair. > For gen_load, however, i can delay the generation using something like > > static inline TCGv_ptr get_ptr0(DisasContext *s) > { > if (s->ptr0) { > return s->ptr0; > } > s->ptr0 = tcg_temp_new_ptr(); > tcg_gen_add(s->ptr0, cpu_env, ...); > return s->ptr0; > } Sure. > For gen_writeback, keeping gen_writeback eliminates duplicated code > and keeps the phases of disas_insn_new separated, so I prefer it > slightly. For now I'd rather leave it as is; with the above get_ptr0() > function that creates s->ptr0 lazily, perhaps gen_writeback() could do > it only if s->ptr0 is set (suggesting that a helper was used), while > gvec helpers would use the oprsz be said for keeping the initial implementation simple of course, > especially since it's already slightly better than the code produced > by the existing decoder. Also fair. Let's ignore the max argument for now, and address it in a subsequent phase, where we also convert more operations to gvec. >> This could also be >> >> tcg_gen_gvec_dup_i64(MO_64, offset, 8, sse_vec_max_len, s->T1); > > Yeah, it can be something like > > case MO_32: > tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1); > tcg_gen_gvec_dup_i32(MO_32, decode->op[0].offset, 4, vec_len, > s->tmp3_i32); > break; Actually, this doesn't work, because minimum vector size is 8. This will hit the assert in check_size_align(). I've just realized that we can't just extend i32 to i64, as I was suggesting, because that will fall foul of big-endian host (L(0) is at the top half of Q(0)). So best to keep your zero + store. r~