[Qemu-devel] [PATCH] Fix GT64120 PCI IO mapping update

[Qemu-devel] [PATCH] Fix GT64120 PCI IO mapping update

[Aurelien Jarno]

Hi,

The patch below fixes a bug when updating the GT64120 PCI IO mapping.
The old addresses should be unmapped first before trying to setup a new
one.

Bye,
Aurelien


Index: hw/gt64xxx.c
===================================================================
RCS file: /sources/qemu/qemu/hw/gt64xxx.c,v
retrieving revision 1.4
diff -u -d -p -r1.4 gt64xxx.c
--- hw/gt64xxx.c	31 Jan 2007 12:02:12 -0000	1.4
+++ hw/gt64xxx.c	28 Feb 2007 11:07:45 -0000
@@ -222,18 +222,24 @@ typedef PCIHostState GT64120PCIState;
 typedef struct GT64120State {
     GT64120PCIState *pci;
     uint32_t regs[GT_REGS];
+    target_phys_addr_t PCI0IO_start;
+    target_phys_addr_t PCI0IO_length;
 } GT64120State;
 
 static void gt64120_pci_mapping(GT64120State *s)
 {
-    target_phys_addr_t start, length;		   
-
     /* Update IO mapping */
     if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD])
     {
-      start = s->regs[GT_PCI0IOLD] << 21;
-      length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
-      isa_mmio_init(start, length);
+      /* Unmap old IO address */	    
+      if (s->PCI0IO_length)
+      {
+        cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED);	     
+      }
+      /* Map new IO address */
+      s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
+      s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
+      isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length);
     }
 }
 
-- 
  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   aurel32@debian.org         | aurelien@aurel32.net
   `-    people.debian.org/~aurel32 | www.aurel32.net

Re: [Qemu-devel] [PATCH] Fix GT64120 PCI IO mapping update

[Stefan Weil]

[-- Attachment #1: Type: text/plain, Size: 1192 bytes --]

Hi,

here are some more patches for the GT64120 PCI:

* Fix the device id (byte order was swapped for mips and mipsel).
  Now lspci shows the correct device name (for any endianess).

* Fix the byte order for GT64120 PCI configuration (was swapped
  for mips). Now lspci shows the GT64120 device for big endian, too.

* Fix the initial value of the CPU configuration register.
  For big endian machines, it was set to 0x800, but
  bit 12 is the endian bit, so maybe 0x1000 is better.
  I see no difference for Linux, so obviously nobody reads
  this bit value. It should be read by the emulation (currently
  it is not)...

There remain several issues even with these patches (little and big endian):
Malta cannot allocate some PCI address space even for the standard
configuration. See dpkg.txt and lspci.txt for the error messages.

Perhaps somebody can contribute the output of dmesg, lspci -v and
lspci -x for real hardware so I have a reference for the emulation?

Regards
Stefan


Aurelien Jarno schrieb:
> Hi,
>
> The patch below fixes a bug when updating the GT64120 PCI IO mapping.
> The old addresses should be unmapped first before trying to setup a new
> one.
>
> Bye,
> Aurelien

[-- Attachment #2: gt64xxx.patch --]
[-- Type: text/x-diff, Size: 1751 bytes --]

Index: hw/gt64xxx.c
===================================================================
RCS file: /sources/qemu/qemu/hw/gt64xxx.c,v
retrieving revision 1.7
diff -u -b -B -r1.7 gt64xxx.c
--- hw/gt64xxx.c	7 Apr 2007 18:14:41 -0000	1.7
+++ hw/gt64xxx.c	15 Apr 2007 12:26:55 -0000
@@ -550,7 +550,7 @@
 #ifdef TARGET_WORDS_BIGENDIAN
     s->regs[GT_CPU]           = 0x00000000;
 #else
-    s->regs[GT_CPU]           = 0x00000800;
+    s->regs[GT_CPU]           = 0x00001000;
 #endif
     s->regs[GT_MULTI]         = 0x00000000;
 
@@ -608,6 +608,25 @@
     gt64120_pci_mapping(s);
 }
 
+static uint32_t gt64120_read_config(PCIDevice *d, 
+                                uint32_t address, int len)
+{
+    uint32_t val = pci_default_read_config(d, address, len);
+#ifdef TARGET_WORDS_BIGENDIAN
+    val = bswap32(val);
+#endif
+    return val;
+}
+
+static void gt64120_write_config(PCIDevice *d, 
+                                 uint32_t address, uint32_t val, int len)
+{
+#ifdef TARGET_WORDS_BIGENDIAN
+    val = bswap32(val);
+#endif
+    pci_default_write_config(d, address, val, len);
+}
+
 PCIBus *pci_gt64120_init(qemu_irq *pic)
 {
     GT64120State *s;
@@ -626,12 +645,12 @@
     cpu_register_physical_memory(0x1be00000LL, 0x1000, gt64120);
 
     d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),
-                            0, NULL, NULL);
+                            0, gt64120_read_config, gt64120_write_config);
 
     d->config[0x00] = 0xab; // vendor_id
     d->config[0x01] = 0x11;
-    d->config[0x02] = 0x46; // device_id
-    d->config[0x03] = 0x20;
+    d->config[0x02] = 0x20; // device_id
+    d->config[0x03] = 0x46;
     d->config[0x04] = 0x06;
     d->config[0x05] = 0x00;
     d->config[0x06] = 0x80;

[-- Attachment #3: dmesg.txt --]
[-- Type: text/plain, Size: 10410 bytes --]

[42949372.960000] Linux version 2.6.20 (2.6.20-1) (ar7@linux) (gcc version 4.1.2 20061115 (prerelease) (Debian 4.1.1-21)) #1 SMP Sat Apr 14 18:07:32 CEST 2007
[42949372.960000] CPU revision is: 00019000
[42949372.960000] Determined physical RAM map:
[42949372.960000]  memory: 00001000 @ 00000000 (reserved)
[42949372.960000]  memory: 000ef000 @ 00001000 (ROM data)
[42949372.960000]  memory: 003ba000 @ 000f0000 (reserved)
[42949372.960000]  memory: 0fb56000 @ 004aa000 (usable)
[42949372.960000] Initrd not found or empty - disabling initrd
[42949372.960000] On node 0 totalpages: 65536
[42949372.960000]   DMA zone: 512 pages used for memmap
[42949372.960000]   DMA zone: 0 pages reserved
[42949372.960000]   DMA zone: 65024 pages, LIFO batch:15
[42949372.960000]   Normal zone: 0 pages used for memmap
[42949372.960000] Built 1 zonelists.  Total pages: 65024
[42949372.960000] Kernel command line: debug root=/dev/nfs rw ip=::::malta-le::dhcp console=ttyS0,38400n8r
[42949372.960000] 1 MIPSR2 register sets available
[42949372.960000] Primary instruction cache 2kB, physically tagged, 2-way, linesize 16 bytes.
[42949372.960000] Primary data cache 2kB, 2-way, linesize 16 bytes.
[42949372.960000] Synthesized TLB refill handler (23 instructions).
[42949372.960000] Synthesized TLB load handler fastpath (37 instructions).
[42949372.960000] Synthesized TLB store handler fastpath (37 instructions).
[42949372.960000] Synthesized TLB modify handler fastpath (36 instructions).
[42949372.960000] PID hash table entries: 1024 (order: 10, 4096 bytes)
[42949372.960000] CPU frequency 200.01 MHz
[42949372.960000] Using 100.006 MHz high precision timer.
[42949372.960000] Console: colour dummy device 80x25
[42949372.970000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
[42949372.980000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
[42949373.010000] Memory: 254976k/257368k available (2766k kernel code, 2288k reserved, 625k data, 180k init, 0k highmem)
[42949373.020000] Calibrating delay loop... 419.43 BogoMIPS (lpj=2097152)
[42949373.290000] Mount-cache hash table entries: 512
[42949373.300000] Trying to install interrupt handler for IRQ16
[42949373.310000] Trying to install interrupt handler for IRQ17
[42949373.320000] Brought up 1 CPUs
[42949373.330000] NET: Registered protocol family 16
[42949373.360000] PCI: Scanning bus 0000:00
[42949373.370000] PCI: Found 0000:00:00.0 [11ab/4620] 000580 00
[42949373.370000] PCI: Found 0000:00:0a.0 [8086/7110] 000601 00
[42949373.380000] PCI: Calling quirk 80257ac0 for 0000:00:0a.0
[42949373.380000] PCI: Calling quirk 804709e4 for 0000:00:0a.0
[42949373.390000] PCI: Found 0000:00:0a.1 [8086/7010] 000101 00
[42949373.400000] PCI: Calling quirk 80257ac0 for 0000:00:0a.1
[42949373.410000] 0000:00:0a.1: cannot adjust BAR0 (not I/O)
[42949373.420000] 0000:00:0a.1: cannot adjust BAR1 (not I/O)
[42949373.430000] 0000:00:0a.1: cannot adjust BAR2 (not I/O)
[42949373.440000] 0000:00:0a.1: cannot adjust BAR3 (not I/O)
[42949373.450000] PCI: Found 0000:00:0a.2 [8086/7020] 000c03 00
[42949373.460000] PCI: Calling quirk 80257ac0 for 0000:00:0a.2
[42949373.470000] PCI: Found 0000:00:0a.3 [8086/7113] 000680 00
[42949373.480000] PCI: Calling quirk 80257ac0 for 0000:00:0a.3
[42949373.490000] PCI: Calling quirk 80257c78 for 0000:00:0a.3
[42949373.500000] PCI quirk: region b100-b10f claimed by PIIX4 SMB
[42949373.510000] PCI: Found 0000:00:0b.0 [1022/2000] 000200 00
[42949373.520000] PCI: Found 0000:00:12.0 [1013/00b8] 000300 00
[42949373.530000] PCI: Fixups for bus 0000:00
[42949373.540000] PCI: Bus scan for 0000:00 returning with max=00
[42949373.550000]   got res [12000000:13ffffff] bus [12000000:13ffffff] flags 1208 for BAR 0 of 0000:00:12.0
[42949373.560000] PCI: moved device 0000:00:12.0 resource 0 (1208) to 12000000
[42949373.560000] PCI: Failed to allocate mem resource #1:1000@14000000 for 0000:00:12.0
[42949373.570000]   got res [1000:101f] bus [1000:101f] flags 101 for BAR 4 of 0000:00:0a.2
[42949373.580000] PCI: moved device 0000:00:0a.2 resource 4 (101) to 1000
[42949373.590000]   got res [1020:103f] bus [1020:103f] flags 101 for BAR 0 of 0000:00:0b.0
[42949373.600000] PCI: moved device 0000:00:0b.0 resource 0 (101) to 1020
[42949373.610000] PCI: Failed to allocate mem resource #1:20@14000000 for 0000:00:0b.0
[42949373.620000]   got res [1040:104f] bus [1040:104f] flags 101 for BAR 4 of 0000:00:0a.1
[42949373.630000] PCI: moved device 0000:00:0a.1 resource 4 (101) to 1040
[42949373.630000] PCI: fixup irq: (0000:00:00.0) got 0
[42949373.640000] PCI: fixup irq: (0000:00:0a.0) got 0
[42949373.650000] PCI: fixup irq: (0000:00:0a.1) got 0
[42949373.660000] PCI: fixup irq: (0000:00:0a.2) got 11
[42949373.670000] PCI: fixup irq: (0000:00:0a.3) got 0
[42949373.680000] PCI: fixup irq: (0000:00:0b.0) got 10
[42949373.690000] PCI: fixup irq: (0000:00:12.0) got 10
[42949373.700000] NET: Registered protocol family 2
[42949373.800000] IP route cache hash table entries: 2048 (order: 1, 8192 bytes)
[42949373.810000] TCP established hash table entries: 8192 (order: 4, 65536 bytes)
[42949373.820000] TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
[42949373.830000] TCP: Hash tables configured (established 8192 bind 4096)
[42949373.830000] TCP reno registered
[42949373.870000] VFS: Disk quotas dquot_6.5.1
[42949373.880000] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
[42949373.890000] Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
[42949373.900000] io scheduler noop registered
[42949373.910000] io scheduler anticipatory registered (default)
[42949373.920000] io scheduler deadline registered
[42949373.930000] io scheduler cfq registered
[42949373.940000] PCI: Calling quirk 802580f8 for 0000:00:00.0
[42949373.950000] PCI: Calling quirk 802e8780 for 0000:00:00.0
[42949373.960000] PCI: Calling quirk 802580f8 for 0000:00:0a.0
[42949373.970000] PCI: Calling quirk 802e8780 for 0000:00:0a.0
[42949373.980000] PCI: Calling quirk 802580f8 for 0000:00:0a.1
[42949373.990000] PCI: Calling quirk 802e8780 for 0000:00:0a.1
[42949374.000000] PCI: Calling quirk 802580f8 for 0000:00:0a.2
[42949374.010000] PCI: Calling quirk 802e8780 for 0000:00:0a.2
[42949374.020000] PCI: Calling quirk 802580f8 for 0000:00:0a.3
[42949374.030000] PCI: Calling quirk 802e8780 for 0000:00:0a.3
[42949374.030000] PCI: Calling quirk 802580f8 for 0000:00:0b.0
[42949374.040000] PCI: Calling quirk 802e8780 for 0000:00:0b.0
[42949374.040000] PCI: Calling quirk 802580f8 for 0000:00:12.0
[42949374.050000] PCI: Calling quirk 802e8780 for 0000:00:12.0
[42949374.070000]  RAM (4096 kB) at 0xx12000000, Cirrus Logic chipset on PCI bus
[42949374.070000] cirrusfb: Driver for Cirrus Logic based graphic boards, v2.0-pre2
[42949374.170000] cirrusfb: This board has 4194304 bytes of DRAM memory
[42949374.270000] cirrusfb: This board has 4194304 bytes of DRAM memory
[42949374.280000] Console: switching to colour frame buffer device 80x30
[42949374.530000] rtc: SRM (post-2000) epoch (2000) detected
[42949374.540000] Real Time Clock Driver v1.12ac
[42949374.550000] Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
[42949374.560000] serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16450
[42949374.580000] RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
[42949374.590000] pcnet32.c:v1.33-NAPI 27.Jun.2006 tsbogend@alpha.franken.de
[42949374.610000] PCI: Setting latency timer of device 0000:00:0b.0 to 64
[42949374.610000] pcnet32: PCnet/PCI II 79C970A at 0x1020, 52 54 00 12 34 56 assigned IRQ 10.
[42949374.630000] eth0: registered as PCnet/PCI II 79C970A
[42949374.640000] pcnet32: 1 cards_found.
[42949374.650000] e100: Intel(R) PRO/100 Network Driver, 3.5.17-k2-NAPI
[42949374.660000] e100: Copyright(c) 1999-2006 Intel Corporation
[42949374.670000] Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
[42949374.680000] ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
[42949374.690000] PIIX3: IDE controller at PCI slot 0000:00:0a.1
[42949374.700000] PCI: Enabling device 0000:00:0a.1 (0000 -> 0001)
[42949374.710000] PIIX3: chipset revision 0
[42949374.720000] PIIX3: not 100% native mode: will probe irqs later
[42949374.730000] PIIX3: neither IDE port enabled (BIOS)
[42949374.740000] Probing IDE interface ide0...
[42949375.350000] Probing IDE interface ide1...
[42949376.280000] hdc: QEMU CD-ROM, ATAPI CD/DVD-ROM drive
[42949377.010000] ide1 at 0x170-0x177,0x376 on irq 15
[42949377.020000] hdc: ATAPI 4X CD-ROM drive, 512kB Cache
[42949377.030000] Uniform CD-ROM driver Revision: 3.20
[42949377.030000] physmap platform flash device: 00400000 at 1e000000
[42949377.040000] CFI: Found no physmap-flash.0 device at location zero
[42949377.050000] physmap-flash physmap-flash.0: map_probe failed
[42949377.060000] serio: i8042 KBD port at 0x60,0x64 irq 1
[42949377.070000] serio: i8042 AUX port at 0x60,0x64 irq 12
[42949377.080000] mice: PS/2 mouse device common for all mice
[42949377.190000] input: AT Raw Set 2 keyboard as /class/input/input0
[42949377.200000] TCP cubic registered
[42949377.200000] NET: Registered protocol family 1
[42949377.210000] NET: Registered protocol family 17
[42949377.210000] NET: Registered protocol family 15
[42949377.420000] input: ImExPS/2 Generic Explorer Mouse as /class/input/input1
[42949377.470000] Bridge firewalling registered
[42949377.470000] 802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
[42949377.480000] All bugs added by David S. Miller <davem@redhat.com>
[42949377.500000] Time: MIPS clocksource has been installed.
[42949378.000000] eth0: link up
[42949379.020000] Sending DHCP requests ., OK
[42949379.050000] IP-Config: Got DHCP answer from 10.0.2.2, my address is 10.0.2.15
[42949379.060000] IP-Config: Complete:
[42949379.070000]       device=eth0, addr=10.0.2.15, mask=255.255.255.0, gw=10.0.2.2,
[42949379.080000]      host=malta-le, domain=, nis-domain=(none),
[42949379.090000]      bootserver=10.0.2.2, rootserver=10.0.2.2, rootpath=
[42949379.100000] Looking up port of RPC 100003/2 on 10.0.2.2
[42949379.130000] Looking up port of RPC 100005/1 on 10.0.2.2
[42949379.160000] VFS: Mounted root (nfs filesystem).
[42949379.160000] Freeing prom memory: 956kb freed
[42949379.170000] Freeing firmware memory: 956kb freed
[42949379.190000] Freeing unused kernel memory: 180k freed
[42949379.240000] Algorithmics/MIPS FPU Emulator v1.5

[-- Attachment #4: lspci.txt --]
[-- Type: text/plain, Size: 1377 bytes --]

00:00.0 Memory controller: Marvell Technology Group Ltd. GT-64120/64120A/64121A System Controller (rev 10)
	Flags: bus master, medium devsel, latency 64
	Memory at <ignored> (32-bit, non-prefetchable)
	Memory at <ignored> (32-bit, non-prefetchable)
	Memory at <ignored> (32-bit, non-prefetchable)
	Memory at <ignored> (32-bit, non-prefetchable)
	Memory at <ignored> (32-bit, non-prefetchable)

00:0a.0 ISA bridge: Intel Corporation 82371AB/EB/MB PIIX4 ISA
	Flags: bus master, medium devsel, latency 0

00:0a.1 IDE interface: Intel Corporation 82371SB PIIX3 IDE [Natoma/Triton II] (prog-if 80 [Master])
	Flags: medium devsel
	[virtual] I/O ports at 01f0 [size=8]
	[virtual] I/O ports at 03f4
	[virtual] I/O ports at 0170 [size=8]
	[virtual] I/O ports at 0374
	I/O ports at 1040 [size=16]

00:0a.2 USB Controller: Intel Corporation 82371SB PIIX3 USB [Natoma/Triton II] (rev 01) (prog-if 00 [UHCI])
	Flags: fast devsel, IRQ 11
	I/O ports at 1000 [disabled] [size=32]

00:0a.3 Bridge: Intel Corporation 82371AB/EB/MB PIIX4 ACPI
	Flags: fast devsel

00:0b.0 Ethernet controller: Advanced Micro Devices [AMD] 79c970 [PCnet32 LANCE] (rev 10)
	Flags: bus master, medium devsel, latency 64, IRQ 10
	I/O ports at 1020 [size=32]

00:12.0 VGA compatible controller: Cirrus Logic GD 5446 (prog-if 00 [VGA])
	Flags: fast devsel, IRQ 10
	Memory at 12000000 (32-bit, prefetchable) [size=32M]

Re: [Qemu-devel] [PATCH] Fix GT64120 PCI IO mapping update

[Aurelien Jarno]

On Sun, Apr 15, 2007 at 03:07:38PM +0200, Stefan Weil wrote:
> Hi,
> 
> here are some more patches for the GT64120 PCI:
> 
> * Fix the device id (byte order was swapped for mips and mipsel).
>   Now lspci shows the correct device name (for any endianess).
> 
> * Fix the byte order for GT64120 PCI configuration (was swapped
>   for mips). Now lspci shows the GT64120 device for big endian, too.
> 
> * Fix the initial value of the CPU configuration register.
>   For big endian machines, it was set to 0x800, but
>   bit 12 is the endian bit, so maybe 0x1000 is better.
>   I see no difference for Linux, so obviously nobody reads
>   this bit value. It should be read by the emulation (currently
>   it is not)...

Good catch!

> There remain several issues even with these patches (little and big endian):
> Malta cannot allocate some PCI address space even for the standard
> configuration. See dpkg.txt and lspci.txt for the error messages.

I don't have such messages in the build log. I am using a 2.6.18 kernel,
whereas you are using a 2.6.20. May that explain the difference? Or
maybe you have enable some debug flags in the kernel?

The problem may be due to the fact YAMON (and probably redboot) 
initializes the GT64120 BAR registers to different values than the
default one. As we are booting the kernel directly, the values are
wrong. The patch below does the same thing as YAMON in the pseudo
bootloader.

Cheers,
Aurelien


Index: hw/mips_malta.c
===================================================================
RCS file: /sources/qemu/qemu/hw/mips_malta.c,v
retrieving revision 1.23
diff -u -d -p -r1.23 mips_malta.c
--- hw/mips_malta.c	7 Apr 2007 18:14:41 -0000	1.23
+++ hw/mips_malta.c	15 Apr 2007 14:40:34 -0000
@@ -548,6 +548,50 @@ static void write_bootloader (CPUState *
     stl_raw(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff));         /* ori a2, a2, low(ENVP_ADDR + 8) */
     stl_raw(p++, 0x3c070000 | (env->ram_size >> 16));              /* lui a3, high(env->ram_size) */
     stl_raw(p++, 0x34e70000 | (env->ram_size & 0xffff));           /* ori a3, a3, low(env->ram_size) */
+
+    /* Load BAR registers as done by YAMON */
+    stl_raw(p++, 0x3c091be0);                                      /* lui t1, 0x1be0 */
+
+#ifdef TARGET_WORDS_BIGENDIAN
+    stl_raw(p++, 0x3c08c000);                                      /* lui t0, 0xc000 */
+#else
+    stl_raw(p++, 0x340800c0);                                      /* ori t0, r0, 0x00c0 */
+#endif
+    stl_raw(p++, 0xad280048);                                      /* sw t0, 0x0048(t1) */
+#ifdef TARGET_WORDS_BIGENDIAN
+    stl_raw(p++, 0x3c084000);                                      /* lui t0, 0x4000 */
+#else
+    stl_raw(p++, 0x34080040);                                      /* ori t0, r0, 0x0040 */
+#endif
+    stl_raw(p++, 0xad280050);                                      /* sw t0, 0x0050(t1) */
+
+#ifdef TARGET_WORDS_BIGENDIAN
+    stl_raw(p++, 0x3c088000);                                      /* lui t0, 0x8000 */
+#else
+    stl_raw(p++, 0x34080080);                                      /* ori t0, r0, 0x0080 */
+#endif
+    stl_raw(p++, 0xad280058);                                      /* sw t0, 0x0058(t1) */
+#ifdef TARGET_WORDS_BIGENDIAN
+    stl_raw(p++, 0x3c083f00);                                      /* lui t0, 0x3f00 */
+#else
+    stl_raw(p++, 0x3408003f);                                      /* ori t0, r0, 0x003f */
+#endif
+    stl_raw(p++, 0xad280060);                                      /* sw t0, 0x0060(t1) */
+
+#ifdef TARGET_WORDS_BIGENDIAN
+    stl_raw(p++, 0x3c08c100);                                      /* lui t0, 0xc100 */
+#else
+    stl_raw(p++, 0x340800c1);                                      /* ori t0, r0, 0x00c1 */
+#endif
+    stl_raw(p++, 0xad280080);                                      /* sw t0, 0x0080(t1) */
+#ifdef TARGET_WORDS_BIGENDIAN
+    stl_raw(p++, 0x3c085e00);                                      /* lui t0, 0x5e00 */
+#else
+    stl_raw(p++, 0x3408005e);                                      /* ori t0, r0, 0x005e */
+#endif
+    stl_raw(p++, 0xad280088);                                      /* sw t0, 0x0088(t1) */
+
+    /* Jump to kernel code */
     stl_raw(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff));    /* lui ra, high(kernel_entry) */
     stl_raw(p++, 0x37ff0000 | (kernel_entry & 0xffff));            /* ori ra, ra, low(kernel_entry) */
     stl_raw(p++, 0x03e00008);                                      /* jr ra */

-- 
  .''`.  Aurelien Jarno	            | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   aurel32@debian.org         | aurelien@aurel32.net
   `-    people.debian.org/~aurel32 | www.aurel32.net

Re: [Qemu-devel] [PATCH] Fix GT64120 PCI IO mapping update

[Stefan Weil]

Thanks. Now QEMU/Malta works better than ever :-)
Below is a small change which is needed for your patch.

Regards
Stefan

Aurelien Jarno schrieb:
> Index: hw/mips_malta.c
> ===================================================================
> RCS file: /sources/qemu/qemu/hw/mips_malta.c,v
> retrieving revision 1.23
> diff -u -d -p -r1.23 mips_malta.c
> --- hw/mips_malta.c	7 Apr 2007 18:14:41 -0000	1.23
> +++ hw/mips_malta.c	15 Apr 2007 14:40:34 -0000
> @@ -548,6 +548,50 @@ static void write_bootloader (CPUState *
>      stl_raw(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff));         /* ori a2, a2, low(ENVP_ADDR + 8) */
>      stl_raw(p++, 0x3c070000 | (env->ram_size >> 16));              /* lui a3, high(env->ram_size) */
>      stl_raw(p++, 0x34e70000 | (env->ram_size & 0xffff));           /* ori a3, a3, low(env->ram_size) */
> +
> +    /* Load BAR registers as done by YAMON */
> +    stl_raw(p++, 0x3c091be0);                                      /* lui t1, 0x1be0 */
+    stl_raw(p++, 0x3c09bbe0);                                      /* lui t1, 0xbbe0 */

> +
> +#ifdef TARGET_WORDS_BIGENDIAN
> +    stl_raw(p++, 0x3c08c000);                                      /* lui t0, 0xc000 */
> +#else
> +    stl_raw(p++, 0x340800c0);                                      /* ori t0, r0, 0x00c0 */
> +#endif
> +    stl_raw(p++, 0xad280048);                                      /* sw t0, 0x0048(t1) */
> +#ifdef TARGET_WORDS_BIGENDIAN
> +    stl_raw(p++, 0x3c084000);                                      /* lui t0, 0x4000 */
> +#else
> +    stl_raw(p++, 0x34080040);                                      /* ori t0, r0, 0x0040 */
> +#endif
> +    stl_raw(p++, 0xad280050);                                      /* sw t0, 0x0050(t1) */
> +
> +#ifdef TARGET_WORDS_BIGENDIAN
> +    stl_raw(p++, 0x3c088000);                                      /* lui t0, 0x8000 */
> +#else
> +    stl_raw(p++, 0x34080080);                                      /* ori t0, r0, 0x0080 */
> +#endif
> +    stl_raw(p++, 0xad280058);                                      /* sw t0, 0x0058(t1) */
> +#ifdef TARGET_WORDS_BIGENDIAN
> +    stl_raw(p++, 0x3c083f00);                                      /* lui t0, 0x3f00 */
> +#else
> +    stl_raw(p++, 0x3408003f);                                      /* ori t0, r0, 0x003f */
> +#endif
> +    stl_raw(p++, 0xad280060);                                      /* sw t0, 0x0060(t1) */
> +
> +#ifdef TARGET_WORDS_BIGENDIAN
> +    stl_raw(p++, 0x3c08c100);                                      /* lui t0, 0xc100 */
> +#else
> +    stl_raw(p++, 0x340800c1);                                      /* ori t0, r0, 0x00c1 */
> +#endif
> +    stl_raw(p++, 0xad280080);                                      /* sw t0, 0x0080(t1) */
> +#ifdef TARGET_WORDS_BIGENDIAN
> +    stl_raw(p++, 0x3c085e00);                                      /* lui t0, 0x5e00 */
> +#else
> +    stl_raw(p++, 0x3408005e);                                      /* ori t0, r0, 0x005e */
> +#endif
> +    stl_raw(p++, 0xad280088);                                      /* sw t0, 0x0088(t1) */
> +
> +    /* Jump to kernel code */
>      stl_raw(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff));    /* lui ra, high(kernel_entry) */
>      stl_raw(p++, 0x37ff0000 | (kernel_entry & 0xffff));            /* ori ra, ra, low(kernel_entry) */
>      stl_raw(p++, 0x03e00008);                                      /* jr ra */
>

Re: [Qemu-devel] [PATCH] Fix GT64120 PCI IO mapping update

[Stefan Weil]

[-- Attachment #1: Type: text/plain, Size: 1676 bytes --]

Hi,

Aurelien's patch is still missing in CVS HEAD.

I resend it here with a small address fix.

Please add this patch to CVS. It is needed for PCI devices like
those in eepro100.c.

Thank you

Stefan


Aurelien Jarno schrieb:
> I don't have such messages in the build log. I am using a 2.6.18 kernel,
> whereas you are using a 2.6.20. May that explain the difference? Or
> maybe you have enable some debug flags in the kernel?
I have enabled the debug flag for PCI.
>
> The problem may be due to the fact YAMON (and probably redboot)
> initializes the GT64120 BAR registers to different values than the
> default one. As we are booting the kernel directly, the values are
> wrong. The patch below does the same thing as YAMON in the pseudo
> bootloader.
... and it works!
>
> Cheers,
> Aurelien
>
>
> Index: hw/mips_malta.c
> ===================================================================
> RCS file: /sources/qemu/qemu/hw/mips_malta.c,v
> retrieving revision 1.23
> diff -u -d -p -r1.23 mips_malta.c
> --- hw/mips_malta.c 7 Apr 2007 18:14:41 -0000 1.23
> +++ hw/mips_malta.c 15 Apr 2007 14:40:34 -0000
> @@ -548,6 +548,50 @@ static void write_bootloader (CPUState *
> stl_raw(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2,
> low(ENVP_ADDR + 8) */
> stl_raw(p++, 0x3c070000 | (env->ram_size >> 16)); /* lui a3,
> high(env->ram_size) */
> stl_raw(p++, 0x34e70000 | (env->ram_size & 0xffff)); /* ori a3, a3,
> low(env->ram_size) */
> +
> + /* Load BAR registers as done by YAMON */
> + stl_raw(p++, 0x3c091be0); /* lui t1, 0x1be0 */
I had to replace 0x1be0 by 0xbbe0.
> +
> +#ifdef TARGET_WORDS_BIGENDIAN
> + stl_raw(p++, 0x3c08c000); /* lui t0, 0xc000 */


[-- Attachment #2: mips_malta.patch --]
[-- Type: text/x-diff, Size: 3010 bytes --]

Index: hw/mips_malta.c
===================================================================
RCS file: /sources/qemu/qemu/hw/mips_malta.c,v
retrieving revision 1.23
diff -u -b -B -r1.23 mips_malta.c
--- hw/mips_malta.c	7 Apr 2007 18:14:41 -0000	1.23
+++ hw/mips_malta.c	18 Apr 2007 17:26:44 -0000
@@ -548,6 +548,50 @@
     stl_raw(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff));         /* ori a2, a2, low(ENVP_ADDR + 8) */
     stl_raw(p++, 0x3c070000 | (env->ram_size >> 16));              /* lui a3, high(env->ram_size) */
     stl_raw(p++, 0x34e70000 | (env->ram_size & 0xffff));           /* ori a3, a3, low(env->ram_size) */
+
+    /* Load BAR registers as done by YAMON */
+    stl_raw(p++, 0x3c09bbe0);                                      /* lui t1, 0xbbe0 */
+
+#ifdef TARGET_WORDS_BIGENDIAN
+    stl_raw(p++, 0x3c08c000);                                      /* lui t0, 0xc000 */
+#else
+    stl_raw(p++, 0x340800c0);                                      /* ori t0, r0, 0x00c0 */
+#endif
+    stl_raw(p++, 0xad280048);                                      /* sw t0, 0x0048(t1) */
+#ifdef TARGET_WORDS_BIGENDIAN
+    stl_raw(p++, 0x3c084000);                                      /* lui t0, 0x4000 */
+#else
+    stl_raw(p++, 0x34080040);                                      /* ori t0, r0, 0x0040 */
+#endif
+    stl_raw(p++, 0xad280050);                                      /* sw t0, 0x0050(t1) */
+
+#ifdef TARGET_WORDS_BIGENDIAN
+    stl_raw(p++, 0x3c088000);                                      /* lui t0, 0x8000 */
+#else
+    stl_raw(p++, 0x34080080);                                      /* ori t0, r0, 0x0080 */
+#endif
+    stl_raw(p++, 0xad280058);                                      /* sw t0, 0x0058(t1) */
+#ifdef TARGET_WORDS_BIGENDIAN
+    stl_raw(p++, 0x3c083f00);                                      /* lui t0, 0x3f00 */
+#else
+    stl_raw(p++, 0x3408003f);                                      /* ori t0, r0, 0x003f */
+#endif
+    stl_raw(p++, 0xad280060);                                      /* sw t0, 0x0060(t1) */
+
+#ifdef TARGET_WORDS_BIGENDIAN
+    stl_raw(p++, 0x3c08c100);                                      /* lui t0, 0xc100 */
+#else
+    stl_raw(p++, 0x340800c1);                                      /* ori t0, r0, 0x00c1 */
+#endif
+    stl_raw(p++, 0xad280080);                                      /* sw t0, 0x0080(t1) */
+#ifdef TARGET_WORDS_BIGENDIAN
+    stl_raw(p++, 0x3c085e00);                                      /* lui t0, 0x5e00 */
+#else
+    stl_raw(p++, 0x3408005e);                                      /* ori t0, r0, 0x005e */
+#endif
+    stl_raw(p++, 0xad280088);                                      /* sw t0, 0x0088(t1) */
+
+    /* Jump to kernel code */
     stl_raw(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff));    /* lui ra, high(kernel_entry) */
     stl_raw(p++, 0x37ff0000 | (kernel_entry & 0xffff));            /* ori ra, ra, low(kernel_entry) */
     stl_raw(p++, 0x03e00008);                                      /* jr ra */