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From: Shameerali Kolothum Thodi via <qemu-devel@nongnu.org>
To: "eric.auger@redhat.com" <eric.auger@redhat.com>,
	"qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
	"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "peter.maydell@linaro.org" <peter.maydell@linaro.org>,
	"jgg@nvidia.com" <jgg@nvidia.com>,
	"nicolinc@nvidia.com" <nicolinc@nvidia.com>,
	"ddutile@redhat.com" <ddutile@redhat.com>,
	"berrange@redhat.com" <berrange@redhat.com>,
	"nathanc@nvidia.com" <nathanc@nvidia.com>,
	"mochs@nvidia.com" <mochs@nvidia.com>,
	"smostafa@google.com" <smostafa@google.com>,
	Linuxarm <linuxarm@huawei.com>,
	"Wangzhou (B)" <wangzhou1@hisilicon.com>,
	jiangkunkun <jiangkunkun@huawei.com>,
	"Jonathan Cameron" <jonathan.cameron@huawei.com>,
	"zhangfei.gao@linaro.org" <zhangfei.gao@linaro.org>
Subject: RE: [PATCH v3 1/6] hw/arm/smmuv3: Check SMMUv3 has PCIe Root Complex association
Date: Thu, 5 Jun 2025 11:15:06 +0000	[thread overview]
Message-ID: <463538bc608e4d04940e2122ca5e393f@huawei.com> (raw)
In-Reply-To: <cb2a688d-fbf2-497e-8baf-f28352766105@redhat.com>



> -----Original Message-----
> From: Eric Auger <eric.auger@redhat.com>
> Sent: Thursday, June 5, 2025 11:02 AM
> To: Shameerali Kolothum Thodi
> <shameerali.kolothum.thodi@huawei.com>; qemu-arm@nongnu.org;
> qemu-devel@nongnu.org
> Cc: peter.maydell@linaro.org; jgg@nvidia.com; nicolinc@nvidia.com;
> ddutile@redhat.com; berrange@redhat.com; nathanc@nvidia.com;
> mochs@nvidia.com; smostafa@google.com; Linuxarm
> <linuxarm@huawei.com>; Wangzhou (B) <wangzhou1@hisilicon.com>;
> jiangkunkun <jiangkunkun@huawei.com>; Jonathan Cameron
> <jonathan.cameron@huawei.com>; zhangfei.gao@linaro.org
> Subject: Re: [PATCH v3 1/6] hw/arm/smmuv3: Check SMMUv3 has PCIe Root
> Complex association
> 
> > shouldn't you check as well that !pci_bus_bypass_iommu(bus)?
> 
> I see you do the check in 6/6 and I think this is the correct way because in
> case of legacy SMMU it is allowed to have pci_bus_bypass_iommu set on
> the root bus to let the SMMU apply only on pxb buses only. So please
> ignore this comment.

Yes. It is to keep the existing behavior for legacy SMMUv3.

Thanks,
Shameer

  reply	other threads:[~2025-06-05 11:15 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-02 15:41 [PATCH v3 0/6] hw/arm/virt: Add support for user creatable SMMUv3 device Shameer Kolothum via
2025-06-02 15:41 ` [PATCH v3 1/6] hw/arm/smmuv3: Check SMMUv3 has PCIe Root Complex association Shameer Kolothum via
2025-06-05  9:13   ` Eric Auger
2025-06-05  9:53   ` Eric Auger
2025-06-05 10:02     ` Eric Auger via
2025-06-05 11:15       ` Shameerali Kolothum Thodi via [this message]
2025-06-05 10:55   ` Igor Mammedov
2025-06-05 11:29     ` Shameerali Kolothum Thodi via
2025-06-05 12:19       ` Igor Mammedov
2025-06-05 12:36         ` Shameerali Kolothum Thodi via
2025-06-05 13:05           ` Igor Mammedov
2025-06-02 15:41 ` [PATCH v3 2/6] hw/arm/virt-acpi-build: Re-arrange SMMUv3 IORT build Shameer Kolothum via
2025-06-05  9:39   ` Eric Auger
2025-06-05 11:10     ` Shameerali Kolothum Thodi via
2025-06-02 15:41 ` [PATCH v3 3/6] hw/arm/virt-acpi-build: Update IORT for multiple smmuv3 devices Shameer Kolothum via
2025-06-05  9:57   ` Eric Auger
2025-06-05 11:14     ` Shameerali Kolothum Thodi via
2025-06-02 15:41 ` [PATCH v3 4/6] hw/arm/virt: Factor out common SMMUV3 dt bindings code Shameer Kolothum via
2025-06-02 15:41 ` [PATCH v3 5/6] hw/arm/virt: Add an SMMU_IO_LEN macro Shameer Kolothum via
2025-06-02 15:41 ` [PATCH v3 6/6] hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation Shameer Kolothum via
2025-06-05 12:45   ` Eric Auger
2025-06-05  2:02 ` [PATCH v3 0/6] hw/arm/virt: Add support for user creatable SMMUv3 device Nathan Chen
2025-06-05  2:34   ` Donald Dutile
2025-06-05 17:58     ` Nathan Chen
2025-06-05 20:58       ` Donald Dutile

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