From: Aurelien Jarno <aurelien@aurel32.net>
To: Thiemo Seufer <ths@networkno.de>
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH, MIPS64] Fix Status_rw_bitmask values
Date: Fri, 08 Jun 2007 12:02:07 +0200 [thread overview]
Message-ID: <4669291F.2050603@aurel32.net> (raw)
In-Reply-To: <20070605135017.GA18315@networkno.de>
Thiemo Seufer a écrit :
> Aurelien Jarno wrote:
>> Hi all,
>>
>> The patch below fixes the Status_rw_bitmask values for 64-bit CPUs:
>> - Reverse endianess is currently not implemented, the RE bit should
>> not be writable.
>
> OTOH, those CPUs support RE, that's why I left the bit writable.
> I think you'll have to boot RiscOS to check the difference, I don't
> know of any other user. :-)
Ok, I see. The best would clearly to implement that.
>> - 64-bit is implemented, the PX bit should be writable.
>
> The current version is correct, R4000 and 5K don't implement PX, the
> 20Kc and later CPUs do.
I don't know about R4000, but the 5K manual (from www.mips.com) clearly
says that this bit is implemented. Also this bit is marked as "required"
in the MIPS64 PRA manual (for both R1 and R2), and the 5K CPU is
presented as a MIPS64R1 CPU.
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
next prev parent reply other threads:[~2007-06-08 10:02 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-06-04 21:37 [Qemu-devel] [PATCH, MIPS64] Fix Status_rw_bitmask values Aurelien Jarno
2007-06-05 13:50 ` Thiemo Seufer
2007-06-08 10:02 ` Aurelien Jarno [this message]
2007-06-08 14:00 ` Thiemo Seufer
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