* [Qemu-devel] [PATCH v3 01/13] target/mips: Add emulation of MMI instruction PCPYH
2019-03-04 15:13 [Qemu-devel] [PATCH v3 00/13] target/mips: Add emulation of data communication MMI instructions Mateja Marjanovic
@ 2019-03-04 15:13 ` Mateja Marjanovic
2019-03-04 20:36 ` Richard Henderson
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 02/13] target/mips: Add emulation of MMI instruction PCPYLD Mateja Marjanovic
` (11 subsequent siblings)
12 siblings, 1 reply; 23+ messages in thread
From: Mateja Marjanovic @ 2019-03-04 15:13 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Add emulation of MMI instruction PCPYH. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
---
target/mips/translate.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 65 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 364bd6d..c62787d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24348,6 +24348,68 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
* PEXTUW
*/
+/*
+ * PCPYH rd, rt
+ *
+ * Parallel Copy Halfword
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI |0 0 0 0 0| rt | rd | PCPYH | MMI3 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+static void gen_mmi_pcpyh(DisasContext *ctx)
+{
+ uint32_t pd, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ pd = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (unlikely(pd != 0)) {
+ generate_exception_end(ctx, EXCP_RI);
+ } else if (rd == 0) {
+ /* nop */
+ } else if (rt == 0) {
+ tcg_gen_movi_i64(cpu_gpr[rd], 0);
+ tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask = (1ULL << 16) - 1;
+
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+
+ tcg_gen_mov_i64(cpu_gpr[rd], t1);
+
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask);
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+
+ tcg_gen_mov_i64(cpu_mmr[rd], t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+}
+
#endif
@@ -27400,10 +27462,12 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */
case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */
- case MMI_OPC_3_PCPYH: /* TODO: MMI_OPC_3_PCPYH */
case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
break;
+ case MMI_OPC_3_PCPYH:
+ gen_mmi_pcpyh(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI3");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [Qemu-devel] [PATCH v3 01/13] target/mips: Add emulation of MMI instruction PCPYH
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 01/13] target/mips: Add emulation of MMI instruction PCPYH Mateja Marjanovic
@ 2019-03-04 20:36 ` Richard Henderson
0 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2019-03-04 20:36 UTC (permalink / raw)
To: Mateja Marjanovic, qemu-devel; +Cc: arikalo, amarkovic, aurelien
On 3/4/19 7:13 AM, Mateja Marjanovic wrote:
> + uint64_t mask = (1ULL << 16) - 1;
> +
> + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
> + tcg_gen_movi_i64(t1, 0);
> + tcg_gen_or_i64(t1, t0, t1);
> + tcg_gen_shli_i64(t0, t0, 16);
> + tcg_gen_or_i64(t1, t0, t1);
> + tcg_gen_shli_i64(t0, t0, 16);
> + tcg_gen_or_i64(t1, t0, t1);
> + tcg_gen_shli_i64(t0, t0, 16);
> + tcg_gen_or_i64(t1, t0, t1);
I have suggested a better way to write this, twice,
the third time is surely the charm...
tcg_gen_deposit_i64(t0, cpu_gpr[rt], cpu_gpr[rt], 16, 48);
tcg_gen_deposit_i64(t0, t0, t0, 32, 32);
r~
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v3 02/13] target/mips: Add emulation of MMI instruction PCPYLD
2019-03-04 15:13 [Qemu-devel] [PATCH v3 00/13] target/mips: Add emulation of data communication MMI instructions Mateja Marjanovic
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 01/13] target/mips: Add emulation of MMI instruction PCPYH Mateja Marjanovic
@ 2019-03-04 15:13 ` Mateja Marjanovic
2019-03-04 20:37 ` Richard Henderson
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 03/13] target/mips: Add emulation of MMI instruction PCPYUD Mateja Marjanovic
` (10 subsequent siblings)
12 siblings, 1 reply; 23+ messages in thread
From: Mateja Marjanovic @ 2019-03-04 15:13 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, arikalo
Add emulation of MMI instruction PCPYLD. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
---
target/mips/translate.c | 43 ++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c62787d..4756bbb 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24410,6 +24410,45 @@ static void gen_mmi_pcpyh(DisasContext *ctx)
}
}
+/*
+ * PCPYLD rd, rs, rt
+ *
+ * Parallel Copy Lower Doubleword
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI | rs | rt | rd | PCPYLD | MMI2 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+static void gen_mmi_pcpyld(DisasContext *ctx)
+{
+ uint32_t rs, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ rs = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (rd == 0) {
+ /* nop */
+ } else {
+ if (rs == 0) {
+ tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ } else {
+ tcg_gen_mov_i64(cpu_mmr[rd], cpu_gpr[rs]);
+ }
+ if (rt == 0) {
+ tcg_gen_movi_i64(cpu_gpr[rd], 0);
+ } else {
+ if (rd != rt) {
+ tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr[rt]);
+ }
+ }
+ }
+}
+
#endif
@@ -27424,7 +27463,6 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_2_PINTH: /* TODO: MMI_OPC_2_PINTH */
case MMI_OPC_2_PMULTW: /* TODO: MMI_OPC_2_PMULTW */
case MMI_OPC_2_PDIVW: /* TODO: MMI_OPC_2_PDIVW */
- case MMI_OPC_2_PCPYLD: /* TODO: MMI_OPC_2_PCPYLD */
case MMI_OPC_2_PMADDH: /* TODO: MMI_OPC_2_PMADDH */
case MMI_OPC_2_PHMADH: /* TODO: MMI_OPC_2_PHMADH */
case MMI_OPC_2_PAND: /* TODO: MMI_OPC_2_PAND */
@@ -27439,6 +27477,9 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_2_PROT3W: /* TODO: MMI_OPC_2_PROT3W */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI2 */
break;
+ case MMI_OPC_2_PCPYLD:
+ gen_mmi_pcpyld(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI2");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [Qemu-devel] [PATCH v3 03/13] target/mips: Add emulation of MMI instruction PCPYUD
2019-03-04 15:13 [Qemu-devel] [PATCH v3 00/13] target/mips: Add emulation of data communication MMI instructions Mateja Marjanovic
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 01/13] target/mips: Add emulation of MMI instruction PCPYH Mateja Marjanovic
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 02/13] target/mips: Add emulation of MMI instruction PCPYLD Mateja Marjanovic
@ 2019-03-04 15:13 ` Mateja Marjanovic
2019-03-04 20:38 ` Richard Henderson
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 04/13] target/mips: Add emulation of MMI instruction PEXCH Mateja Marjanovic
` (9 subsequent siblings)
12 siblings, 1 reply; 23+ messages in thread
From: Mateja Marjanovic @ 2019-03-04 15:13 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Add emulation of MMI instruction PCPYUD. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
---
target/mips/translate.c | 43 ++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4756bbb..4763e06 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24449,6 +24449,45 @@ static void gen_mmi_pcpyld(DisasContext *ctx)
}
}
+/*
+ * PCPYUD rd, rs, rt
+ *
+ * Parallel Copy Upper Doubleword
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI | rs | rt | rd | PCPYUD | MMI3 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+static void gen_mmi_pcpyud(DisasContext *ctx)
+{
+ uint32_t rs, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ rs = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (rd == 0) {
+ /* nop */
+ } else {
+ if (rs == 0) {
+ tcg_gen_movi_i64(cpu_gpr[rd], 0);
+ } else {
+ tcg_gen_mov_i64(cpu_gpr[rd], cpu_mmr[rs]);
+ }
+ if (rt == 0) {
+ tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ } else {
+ if (rd != rt) {
+ tcg_gen_mov_i64(cpu_mmr[rd], cpu_mmr[rt]);
+ }
+ }
+ }
+}
+
#endif
@@ -27499,7 +27538,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PINTEH: /* TODO: MMI_OPC_3_PINTEH */
case MMI_OPC_3_PMULTUW: /* TODO: MMI_OPC_3_PMULTUW */
case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */
- case MMI_OPC_3_PCPYUD: /* TODO: MMI_OPC_3_PCPYUD */
case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */
case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */
@@ -27509,6 +27547,9 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PCPYH:
gen_mmi_pcpyh(ctx);
break;
+ case MMI_OPC_3_PCPYUD:
+ gen_mmi_pcpyud(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI3");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [Qemu-devel] [PATCH v3 04/13] target/mips: Add emulation of MMI instruction PEXCH
2019-03-04 15:13 [Qemu-devel] [PATCH v3 00/13] target/mips: Add emulation of data communication MMI instructions Mateja Marjanovic
` (2 preceding siblings ...)
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 03/13] target/mips: Add emulation of MMI instruction PCPYUD Mateja Marjanovic
@ 2019-03-04 15:13 ` Mateja Marjanovic
2019-03-04 17:36 ` Aleksandar Markovic
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 05/13] target/mips: Add emulation of MMI instruction PEXCW Mateja Marjanovic
` (8 subsequent siblings)
12 siblings, 1 reply; 23+ messages in thread
From: Mateja Marjanovic @ 2019-03-04 15:13 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Add emulation of MMI instruction PEXCH. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/translate.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 96 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4763e06..9472477 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24488,6 +24488,99 @@ static void gen_mmi_pcpyud(DisasContext *ctx)
}
}
+/*
+ * PEXCH rd, rt
+ *
+ * Parallel Exchange Center Halfword
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI |0 0 0 0 0| rt | rd | PEXCH | MMI3 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+static void gen_mmi_pexch(DisasContext *ctx)
+{
+ uint32_t pd, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ pd = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (unlikely(pd != 0)) {
+ generate_exception_end(ctx, EXCP_RI);
+ } else if (rd == 0) {
+ /* nop */
+ } else if (rt == 0) {
+ tcg_gen_movi_i64(cpu_gpr[rd], 0);
+ tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ } else if (rd == rt) {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask0 = (1ULL << 16) - 1;
+ uint64_t mask1 = mask0 << 16;
+ uint64_t mask2 = mask1 << 16;
+ uint64_t mask3 = (mask2 << 16) | mask0;
+
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2);
+ tcg_gen_shri_i64(t1, t1, 16);
+
+ tcg_gen_andi_i64(cpu_gpr[rd], cpu_gpr[rd], mask3);
+ tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t0);
+ tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t1);
+
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2);
+ tcg_gen_shri_i64(t1, t1, 16);
+
+ tcg_gen_andi_i64(cpu_mmr[rd], cpu_mmr[rd], mask3);
+ tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t0);
+ tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask0 = (1ULL << 16) - 1;
+ uint64_t mask1 = mask0 << 16;
+ uint64_t mask2 = mask1 << 16;
+ uint64_t mask3 = mask2 << 16;
+
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask3);
+ tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t0, t0, t1);
+ tcg_gen_andi_i64(t1, cpu_gpr[rt], mask1);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t0, t0, t1);
+ tcg_gen_andi_i64(t1, cpu_gpr[rt], mask0);
+ tcg_gen_or_i64(t0, t0, t1);
+
+ tcg_gen_mov_i64(cpu_gpr[rd], t0);
+
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask3);
+ tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t0, t0, t1);
+ tcg_gen_andi_i64(t1, cpu_mmr[rt], mask1);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t0, t0, t1);
+ tcg_gen_andi_i64(t1, cpu_mmr[rt], mask0);
+ tcg_gen_or_i64(t0, t0, t1);
+
+ tcg_gen_mov_i64(cpu_mmr[rd], t0);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+}
+
#endif
@@ -27540,7 +27633,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */
case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */
case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
- case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */
case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
break;
@@ -27550,6 +27642,9 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PCPYUD:
gen_mmi_pcpyud(ctx);
break;
+ case MMI_OPC_3_PEXCH:
+ gen_mmi_pexch(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI3");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [Qemu-devel] [PATCH v3 04/13] target/mips: Add emulation of MMI instruction PEXCH
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 04/13] target/mips: Add emulation of MMI instruction PEXCH Mateja Marjanovic
@ 2019-03-04 17:36 ` Aleksandar Markovic
0 siblings, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2019-03-04 17:36 UTC (permalink / raw)
To: Mateja Marjanovic, qemu-devel@nongnu.org
Cc: aurelien@aurel32.net, Aleksandar Rikalo
> From: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
> Subject: [PATCH v3 04/13] target/mips: Add emulation of MMI instruction PEXCH
>
> From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
>
> Add emulation of MMI instruction PEXCH. The emulation is implemented
> using TCG front end operations directly to achieve better performance.
>
> Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
> ---
> target/mips/translate.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 96 insertions(+), 1 deletion(-)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 4763e06..9472477 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -24488,6 +24488,99 @@ static void gen_mmi_pcpyud(DisasContext *ctx)
> }
> }
>
> +/*
> + * PEXCH rd, rt
> + *
> + * Parallel Exchange Center Halfword
The text in the last line should be indented for consistency with previuos\
patches:
* Parallel Exchange Center Halfword
> + *
> + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> + * +-----------+---------+---------+---------+---------+-----------+
> + * | MMI |0 0 0 0 0| rt | rd | PEXCH | MMI3 |
> + * +-----------+---------+---------+---------+---------+-----------+
> + */
> +static void gen_mmi_pexch(DisasContext *ctx)
> +{
> + uint32_t pd, rt, rd;
> + uint32_t opcode;
> +
> + opcode = ctx->opcode;
> +
> + pd = extract32(opcode, 21, 5);
> + rt = extract32(opcode, 16, 5);
> + rd = extract32(opcode, 11, 5);
> +
> + if (unlikely(pd != 0)) {
> + generate_exception_end(ctx, EXCP_RI);
> + } else if (rd == 0) {
> + /* nop */
> + } else if (rt == 0) {
> + tcg_gen_movi_i64(cpu_gpr[rd], 0);
> + tcg_gen_movi_i64(cpu_mmr[rd], 0);
> + } else if (rd == rt) {
> + TCGv_i64 t0 = tcg_temp_new();
> + TCGv_i64 t1 = tcg_temp_new();
> + uint64_t mask0 = (1ULL << 16) - 1;
> + uint64_t mask1 = mask0 << 16;
> + uint64_t mask2 = mask1 << 16;
The last line is clearer this way, IMHO:
uint64_t mask2 = mask0 << 32;
> + uint64_t mask3 = (mask2 << 16) | mask0;
...and this line this way:
uint64_t mask3 = (mask0 << 48) | mask0;
> +
> + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
> + tcg_gen_shli_i64(t0, t0, 16);
> + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2);
> + tcg_gen_shri_i64(t1, t1, 16);
> +
> + tcg_gen_andi_i64(cpu_gpr[rd], cpu_gpr[rd], mask3);
> + tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t0);
> + tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t1);
> +
> + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1);
> + tcg_gen_shli_i64(t0, t0, 16);
> + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2);
> + tcg_gen_shri_i64(t1, t1, 16);
> +
> + tcg_gen_andi_i64(cpu_mmr[rd], cpu_mmr[rd], mask3);
> + tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t0);
> + tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t1);
> +
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + } else {
> + TCGv_i64 t0 = tcg_temp_new();
> + TCGv_i64 t1 = tcg_temp_new();
> + uint64_t mask0 = (1ULL << 16) - 1;
> + uint64_t mask1 = mask0 << 16;
> + uint64_t mask2 = mask1 << 16;
> + uint64_t mask3 = mask2 << 16;
The last two lines are clearer this way:
uint64_t mask2 = mask0 << 32;
uint64_t mask3 = mask0 << 48;
> +
> + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask3);
> + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2);
> + tcg_gen_shri_i64(t1, t1, 16);
> + tcg_gen_or_i64(t0, t0, t1);
> + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask1);
> + tcg_gen_shli_i64(t1, t1, 16);
> + tcg_gen_or_i64(t0, t0, t1);
> + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask0);
> + tcg_gen_or_i64(t0, t0, t1);
> +
> + tcg_gen_mov_i64(cpu_gpr[rd], t0);
> +
> + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask3);
> + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2);
> + tcg_gen_shri_i64(t1, t1, 16);
> + tcg_gen_or_i64(t0, t0, t1);
> + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask1);
> + tcg_gen_shli_i64(t1, t1, 16);
> + tcg_gen_or_i64(t0, t0, t1);
> + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask0);
> + tcg_gen_or_i64(t0, t0, t1);
> +
> + tcg_gen_mov_i64(cpu_mmr[rd], t0);
> +
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + }
> +}
> +
> #endif
>
>
> @@ -27540,7 +27633,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
> case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */
> case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */
> case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
> - case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */
> case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */
> generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
> break;
> @@ -27550,6 +27642,9 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
> case MMI_OPC_3_PCPYUD:
> gen_mmi_pcpyud(ctx);
> break;
> + case MMI_OPC_3_PEXCH:
> + gen_mmi_pexch(ctx);
> + break;
> default:
> MIPS_INVAL("TX79 MMI class MMI3");
> generate_exception_end(ctx, EXCP_RI);
> --
Apart from minor hints above:
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> 2.7.4
>
>
________________________________________
From: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Sent: Monday, March 4, 2019 4:13:16 PM
To: qemu-devel@nongnu.org
Cc: aurelien@aurel32.net; Aleksandar Markovic; Aleksandar Rikalo
Subject: [PATCH v3 04/13] target/mips: Add emulation of MMI instruction PEXCH
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Add emulation of MMI instruction PEXCH. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/translate.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 96 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4763e06..9472477 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24488,6 +24488,99 @@ static void gen_mmi_pcpyud(DisasContext *ctx)
}
}
+/*
+ * PEXCH rd, rt
+ *
+ * Parallel Exchange Center Halfword
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI |0 0 0 0 0| rt | rd | PEXCH | MMI3 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+static void gen_mmi_pexch(DisasContext *ctx)
+{
+ uint32_t pd, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ pd = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (unlikely(pd != 0)) {
+ generate_exception_end(ctx, EXCP_RI);
+ } else if (rd == 0) {
+ /* nop */
+ } else if (rt == 0) {
+ tcg_gen_movi_i64(cpu_gpr[rd], 0);
+ tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ } else if (rd == rt) {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask0 = (1ULL << 16) - 1;
+ uint64_t mask1 = mask0 << 16;
+ uint64_t mask2 = mask1 << 16;
+ uint64_t mask3 = (mask2 << 16) | mask0;
+
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2);
+ tcg_gen_shri_i64(t1, t1, 16);
+
+ tcg_gen_andi_i64(cpu_gpr[rd], cpu_gpr[rd], mask3);
+ tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t0);
+ tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t1);
+
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2);
+ tcg_gen_shri_i64(t1, t1, 16);
+
+ tcg_gen_andi_i64(cpu_mmr[rd], cpu_mmr[rd], mask3);
+ tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t0);
+ tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask0 = (1ULL << 16) - 1;
+ uint64_t mask1 = mask0 << 16;
+ uint64_t mask2 = mask1 << 16;
+ uint64_t mask3 = mask2 << 16;
+
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask3);
+ tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t0, t0, t1);
+ tcg_gen_andi_i64(t1, cpu_gpr[rt], mask1);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t0, t0, t1);
+ tcg_gen_andi_i64(t1, cpu_gpr[rt], mask0);
+ tcg_gen_or_i64(t0, t0, t1);
+
+ tcg_gen_mov_i64(cpu_gpr[rd], t0);
+
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask3);
+ tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t0, t0, t1);
+ tcg_gen_andi_i64(t1, cpu_mmr[rt], mask1);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t0, t0, t1);
+ tcg_gen_andi_i64(t1, cpu_mmr[rt], mask0);
+ tcg_gen_or_i64(t0, t0, t1);
+
+ tcg_gen_mov_i64(cpu_mmr[rd], t0);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+}
+
#endif
@@ -27540,7 +27633,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */
case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */
case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
- case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */
case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
break;
@@ -27550,6 +27642,9 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PCPYUD:
gen_mmi_pcpyud(ctx);
break;
+ case MMI_OPC_3_PEXCH:
+ gen_mmi_pexch(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI3");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v3 05/13] target/mips: Add emulation of MMI instruction PEXCW
2019-03-04 15:13 [Qemu-devel] [PATCH v3 00/13] target/mips: Add emulation of data communication MMI instructions Mateja Marjanovic
` (3 preceding siblings ...)
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 04/13] target/mips: Add emulation of MMI instruction PEXCH Mateja Marjanovic
@ 2019-03-04 15:13 ` Mateja Marjanovic
2019-03-04 17:56 ` Aleksandar Markovic
2019-03-04 20:43 ` Richard Henderson
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 06/13] target/mips: Add emulation of MMI instruction PEXEH Mateja Marjanovic
` (7 subsequent siblings)
12 siblings, 2 replies; 23+ messages in thread
From: Mateja Marjanovic @ 2019-03-04 15:13 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Add emulation of MMI instruction PEXCW. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/translate.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 72 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9472477..64eb10c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24581,6 +24581,75 @@ static void gen_mmi_pexch(DisasContext *ctx)
}
}
+/*
+ * PEXCW rd, rt
+ *
+ * Parallel Exchange Center Word
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI |0 0 0 0 0| rt | rd | PEXCW | MMI3 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+
+static void gen_mmi_pexcw(DisasContext *ctx)
+{
+ uint32_t pd, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ pd = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (unlikely(pd != 0)) {
+ generate_exception_end(ctx, EXCP_RI);
+ } else if (rd == 0) {
+ /* nop */
+ } else if (rt == 0) {
+ tcg_gen_movi_i64(cpu_gpr[rd], 0);
+ tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ } else if (rt == rd) {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask0 = (1ULL << 32) - 1;
+ uint64_t mask1 = mask0 << 32;
+
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
+ tcg_gen_shri_i64(t0, t0, 32);
+ tcg_gen_andi_i64(t1, cpu_mmr[rt], mask0);
+ tcg_gen_shli_i64(t1, t1, 32);
+
+ tcg_gen_andi_i64(cpu_mmr[rd], cpu_mmr[rd], mask1);
+ tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t0);
+
+ tcg_gen_andi_i64(cpu_gpr[rd], cpu_gpr[rd], mask0);
+ tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask0 = (1ULL << 32) - 1;
+ uint64_t mask1 = mask0 << 32;
+
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1);
+ tcg_gen_andi_i64(t1, cpu_gpr[rt], mask1);
+ tcg_gen_shri_i64(t1, t1, 32);
+ tcg_gen_or_i64(cpu_mmr[rd], t0, t1);
+
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask0);
+ tcg_gen_shli_i64(t0, t0, 32);
+ tcg_gen_andi_i64(t1, cpu_gpr[rt], mask0);
+ tcg_gen_or_i64(cpu_gpr[rd], t0, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+}
+
#endif
@@ -27633,7 +27702,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */
case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */
case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
- case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
break;
case MMI_OPC_3_PCPYH:
@@ -27645,6 +27713,9 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PEXCH:
gen_mmi_pexch(ctx);
break;
+ case MMI_OPC_3_PEXCW:
+ gen_mmi_pexcw(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI3");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [Qemu-devel] [PATCH v3 05/13] target/mips: Add emulation of MMI instruction PEXCW
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 05/13] target/mips: Add emulation of MMI instruction PEXCW Mateja Marjanovic
@ 2019-03-04 17:56 ` Aleksandar Markovic
2019-03-04 20:43 ` Richard Henderson
1 sibling, 0 replies; 23+ messages in thread
From: Aleksandar Markovic @ 2019-03-04 17:56 UTC (permalink / raw)
To: Mateja Marjanovic, qemu-devel@nongnu.org
Cc: aurelien@aurel32.net, Aleksandar Rikalo
> From: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
> Subject: [PATCH v3 05/13] target/mips: Add emulation of MMI instruction PEXCW
>
> From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
>
> Add emulation of MMI instruction PEXCW. The emulation is implemented
> using TCG front end operations directly to achieve better performance.
>
> Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
> ---
> target/mips/translate.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 72 insertions(+), 1 deletion(-)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 9472477..64eb10c 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -24581,6 +24581,75 @@ static void gen_mmi_pexch(DisasContext *ctx)
> }
> }
>
> +/*
> + * PEXCW rd, rt
> + *
> + * Parallel Exchange Center Word
> + *
> + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> + * +-----------+---------+---------+---------+---------+-----------+
> + * | MMI |0 0 0 0 0| rt | rd | PEXCW | MMI3 |
> + * +-----------+---------+---------+---------+---------+-----------+
> + */
> +
> +static void gen_mmi_pexcw(DisasContext *ctx)
> +{
> + uint32_t pd, rt, rd;
> + uint32_t opcode;
> +
> + opcode = ctx->opcode;
> +
> + pd = extract32(opcode, 21, 5);
> + rt = extract32(opcode, 16, 5);
> + rd = extract32(opcode, 11, 5);
> +
> + if (unlikely(pd != 0)) {
> + generate_exception_end(ctx, EXCP_RI);
> + } else if (rd == 0) {
> + /* nop */
> + } else if (rt == 0) {
> + tcg_gen_movi_i64(cpu_gpr[rd], 0);
> + tcg_gen_movi_i64(cpu_mmr[rd], 0);
> + } else if (rt == rd) {
> + TCGv_i64 t0 = tcg_temp_new();
> + TCGv_i64 t1 = tcg_temp_new();
> + uint64_t mask0 = (1ULL << 32) - 1;
> + uint64_t mask1 = mask0 << 32;
> +
> + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
> + tcg_gen_shri_i64(t0, t0, 32);
> + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask0);
> + tcg_gen_shli_i64(t1, t1, 32);
> +
> + tcg_gen_andi_i64(cpu_mmr[rd], cpu_mmr[rd], mask1);
> + tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t0);
> +
> + tcg_gen_andi_i64(cpu_gpr[rd], cpu_gpr[rd], mask0);
> + tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t1);
> +
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + } else {
Yes, this block works only for the case rt == rd...
> + TCGv_i64 t0 = tcg_temp_new();
> + TCGv_i64 t1 = tcg_temp_new();
> + uint64_t mask0 = (1ULL << 32) - 1;
> + uint64_t mask1 = mask0 << 32;
> +
> + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1);
> + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask1);
> + tcg_gen_shri_i64(t1, t1, 32);
> + tcg_gen_or_i64(cpu_mmr[rd], t0, t1);
> +
> + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask0);
> + tcg_gen_shli_i64(t0, t0, 32);
> + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask0);
> + tcg_gen_or_i64(cpu_gpr[rd], t0, t1);
> +
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + }
... while this block works only for the case rt != rd.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> +}
> +
> #endif
>
>
> @@ -27633,7 +27702,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
> case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */
> case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */
> case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
> - case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */
> generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
> break;
> case MMI_OPC_3_PCPYH:
> @@ -27645,6 +27713,9 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
> case MMI_OPC_3_PEXCH:
> gen_mmi_pexch(ctx);
> break;
> + case MMI_OPC_3_PEXCW:
> + gen_mmi_pexcw(ctx);
> + break;
> default:
> MIPS_INVAL("TX79 MMI class MMI3");
> generate_exception_end(ctx, EXCP_RI);
> --
> 2.7.4
________________________________________
From: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Sent: Monday, March 4, 2019 4:13:17 PM
To: qemu-devel@nongnu.org
Cc: aurelien@aurel32.net; Aleksandar Markovic; Aleksandar Rikalo
Subject: [PATCH v3 05/13] target/mips: Add emulation of MMI instruction PEXCW
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Add emulation of MMI instruction PEXCW. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/translate.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 72 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9472477..64eb10c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24581,6 +24581,75 @@ static void gen_mmi_pexch(DisasContext *ctx)
}
}
+/*
+ * PEXCW rd, rt
+ *
+ * Parallel Exchange Center Word
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI |0 0 0 0 0| rt | rd | PEXCW | MMI3 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+
+static void gen_mmi_pexcw(DisasContext *ctx)
+{
+ uint32_t pd, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ pd = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (unlikely(pd != 0)) {
+ generate_exception_end(ctx, EXCP_RI);
+ } else if (rd == 0) {
+ /* nop */
+ } else if (rt == 0) {
+ tcg_gen_movi_i64(cpu_gpr[rd], 0);
+ tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ } else if (rt == rd) {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask0 = (1ULL << 32) - 1;
+ uint64_t mask1 = mask0 << 32;
+
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
+ tcg_gen_shri_i64(t0, t0, 32);
+ tcg_gen_andi_i64(t1, cpu_mmr[rt], mask0);
+ tcg_gen_shli_i64(t1, t1, 32);
+
+ tcg_gen_andi_i64(cpu_mmr[rd], cpu_mmr[rd], mask1);
+ tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t0);
+
+ tcg_gen_andi_i64(cpu_gpr[rd], cpu_gpr[rd], mask0);
+ tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask0 = (1ULL << 32) - 1;
+ uint64_t mask1 = mask0 << 32;
+
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1);
+ tcg_gen_andi_i64(t1, cpu_gpr[rt], mask1);
+ tcg_gen_shri_i64(t1, t1, 32);
+ tcg_gen_or_i64(cpu_mmr[rd], t0, t1);
+
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask0);
+ tcg_gen_shli_i64(t0, t0, 32);
+ tcg_gen_andi_i64(t1, cpu_gpr[rt], mask0);
+ tcg_gen_or_i64(cpu_gpr[rd], t0, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+}
+
#endif
@@ -27633,7 +27702,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */
case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */
case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
- case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
break;
case MMI_OPC_3_PCPYH:
@@ -27645,6 +27713,9 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PEXCH:
gen_mmi_pexch(ctx);
break;
+ case MMI_OPC_3_PEXCW:
+ gen_mmi_pexcw(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI3");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [Qemu-devel] [PATCH v3 05/13] target/mips: Add emulation of MMI instruction PEXCW
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 05/13] target/mips: Add emulation of MMI instruction PEXCW Mateja Marjanovic
2019-03-04 17:56 ` Aleksandar Markovic
@ 2019-03-04 20:43 ` Richard Henderson
1 sibling, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2019-03-04 20:43 UTC (permalink / raw)
To: Mateja Marjanovic, qemu-devel; +Cc: arikalo, amarkovic, aurelien
On 3/4/19 7:13 AM, Mateja Marjanovic wrote:
> + } else if (rt == rd) {
> + TCGv_i64 t0 = tcg_temp_new();
> + TCGv_i64 t1 = tcg_temp_new();
> + uint64_t mask0 = (1ULL << 32) - 1;
> + uint64_t mask1 = mask0 << 32;
> +
> + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
> + tcg_gen_shri_i64(t0, t0, 32);
> + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask0);
> + tcg_gen_shli_i64(t1, t1, 32);
> +
> + tcg_gen_andi_i64(cpu_mmr[rd], cpu_mmr[rd], mask1);
> + tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t0);
> +
> + tcg_gen_andi_i64(cpu_gpr[rd], cpu_gpr[rd], mask0);
> + tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t1);
> +
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + } else {
> + TCGv_i64 t0 = tcg_temp_new();
> + TCGv_i64 t1 = tcg_temp_new();
> + uint64_t mask0 = (1ULL << 32) - 1;
> + uint64_t mask1 = mask0 << 32;
> +
> + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1);
> + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask1);
> + tcg_gen_shri_i64(t1, t1, 32);
> + tcg_gen_or_i64(cpu_mmr[rd], t0, t1);
> +
> + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask0);
> + tcg_gen_shli_i64(t0, t0, 32);
> + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask0);
> + tcg_gen_or_i64(cpu_gpr[rd], t0, t1);
> +
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + }
Again, both of these cases can be handled much simpler:
tcg_gen_shri_i64(t0, cpu_gpr[rt], 32);
tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rt], cpu_mmr[rt], 32, 32);
tcg_gen_deposit_i64(cpu_mmu[rd], cpu_mmr[rt], t0, 0, 32);
r~
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v3 06/13] target/mips: Add emulation of MMI instruction PEXEH
2019-03-04 15:13 [Qemu-devel] [PATCH v3 00/13] target/mips: Add emulation of data communication MMI instructions Mateja Marjanovic
` (4 preceding siblings ...)
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 05/13] target/mips: Add emulation of MMI instruction PEXCW Mateja Marjanovic
@ 2019-03-04 15:13 ` Mateja Marjanovic
2019-03-04 18:27 ` Aleksandar Markovic
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 07/13] target/mips: Add emulation of MMI instruction PEXEW Mateja Marjanovic
` (6 subsequent siblings)
12 siblings, 1 reply; 23+ messages in thread
From: Mateja Marjanovic @ 2019-03-04 15:13 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Add emulation of MMI instruction PEXEH. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/translate.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 74 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 64eb10c..01efcde 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24650,6 +24650,77 @@ static void gen_mmi_pexcw(DisasContext *ctx)
}
}
+/*
+ * PEXEH rd, rt
+ *
+ * Parallel Exchange Even Halfword
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI |0 0 0 0 0| rt | rd | PEXEH | MMI2 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+
+static void gen_mmi_pexeh(DisasContext *ctx)
+{
+ uint32_t pd, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ pd = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (unlikely(pd != 0)) {
+ generate_exception_end(ctx, EXCP_RI);
+ } else if (rd == 0) {
+ /* nop */
+ } else if (rt == 0) {
+ tcg_gen_movi_i64(cpu_gpr[rd], 0);
+ tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask0 = (1ULL << 16) - 1;
+ uint64_t mask1 = mask0 << 16;
+ uint64_t mask2 = mask1 << 16;
+ uint64_t mask3 = mask2 << 16;
+
+ tcg_gen_movi_i64(t1, 0);
+
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask0);
+ tcg_gen_shli_i64(t0, t0, 32);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask2);
+ tcg_gen_shri_i64(t0, t0, 32);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask3);
+ tcg_gen_or_i64(t1, t0, t1);
+
+ tcg_gen_mov_i64(cpu_gpr[rd], t1);
+ tcg_gen_movi_i64(t1, 0);
+
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask0);
+ tcg_gen_shli_i64(t0, t0, 32);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask2);
+ tcg_gen_shri_i64(t0, t0, 32);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask3);
+ tcg_gen_or_i64(t1, t0, t1);
+
+ tcg_gen_mov_i64(cpu_mmr[rd], t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+}
+
#endif
@@ -27670,7 +27741,6 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_2_PXOR: /* TODO: MMI_OPC_2_PXOR */
case MMI_OPC_2_PMSUBH: /* TODO: MMI_OPC_2_PMSUBH */
case MMI_OPC_2_PHMSBH: /* TODO: MMI_OPC_2_PHMSBH */
- case MMI_OPC_2_PEXEH: /* TODO: MMI_OPC_2_PEXEH */
case MMI_OPC_2_PREVH: /* TODO: MMI_OPC_2_PREVH */
case MMI_OPC_2_PMULTH: /* TODO: MMI_OPC_2_PMULTH */
case MMI_OPC_2_PDIVBW: /* TODO: MMI_OPC_2_PDIVBW */
@@ -27681,6 +27751,9 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_2_PCPYLD:
gen_mmi_pcpyld(ctx);
break;
+ case MMI_OPC_2_PEXEH:
+ gen_mmi_pexeh(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI2");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [Qemu-devel] [PATCH v3 06/13] target/mips: Add emulation of MMI instruction PEXEH
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 06/13] target/mips: Add emulation of MMI instruction PEXEH Mateja Marjanovic
@ 2019-03-04 18:27 ` Aleksandar Markovic
2019-03-05 12:25 ` Richard Henderson
0 siblings, 1 reply; 23+ messages in thread
From: Aleksandar Markovic @ 2019-03-04 18:27 UTC (permalink / raw)
To: Mateja Marjanovic, qemu-devel@nongnu.org
Cc: aurelien@aurel32.net, Aleksandar Rikalo
> From: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
> Subject: [PATCH v3 06/13] target/mips: Add emulation of MMI instruction PEXEH
>
> From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
>
> Add emulation of MMI instruction PEXEH. The emulation is implemented
> using TCG front end operations directly to achieve better performance.
>
> Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
> ---
> target/mips/translate.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 74 insertions(+), 1 deletion(-)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 64eb10c..01efcde 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -24650,6 +24650,77 @@ static void gen_mmi_pexcw(DisasContext *ctx)
> }
> }
>
> +/*
> + * PEXEH rd, rt
> + *
> + * Parallel Exchange Even Halfword
Indentation...
> + *
> + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> + * +-----------+---------+---------+---------+---------+-----------+
> + * | MMI |0 0 0 0 0| rt | rd | PEXEH | MMI2 |
> + * +-----------+---------+---------+---------+---------+-----------+
> + */
> +
> +static void gen_mmi_pexeh(DisasContext *ctx)
> +{
> + uint32_t pd, rt, rd;
> + uint32_t opcode;
> +
> + opcode = ctx->opcode;
> +
> + pd = extract32(opcode, 21, 5);
> + rt = extract32(opcode, 16, 5);
> + rd = extract32(opcode, 11, 5);
> +
> + if (unlikely(pd != 0)) {
> + generate_exception_end(ctx, EXCP_RI);
> + } else if (rd == 0) {
> + /* nop */
> + } else if (rt == 0) {
> + tcg_gen_movi_i64(cpu_gpr[rd], 0);
> + tcg_gen_movi_i64(cpu_mmr[rd], 0);
> + } else {
> + TCGv_i64 t0 = tcg_temp_new();
> + TCGv_i64 t1 = tcg_temp_new();
> + uint64_t mask0 = (1ULL << 16) - 1;
> + uint64_t mask1 = mask0 << 16;
> + uint64_t mask2 = mask1 << 16;
> + uint64_t mask3 = mask2 << 16;
What about:
uint64_t mask2 = mask0 << 32;
uint64_t mask3 = mask0 << 48;
> +
> + tcg_gen_movi_i64(t1, 0);
> +
The last blank line should be deleted IMO.
> + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask0);
> + tcg_gen_shli_i64(t0, t0, 32);
> + tcg_gen_or_i64(t1, t0, t1);
> + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
> + tcg_gen_or_i64(t1, t0, t1);
> + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask2);
> + tcg_gen_shri_i64(t0, t0, 32);
> + tcg_gen_or_i64(t1, t0, t1);
> + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask3);
> + tcg_gen_or_i64(t1, t0, t1);
> +
> + tcg_gen_mov_i64(cpu_gpr[rd], t1);
> + tcg_gen_movi_i64(t1, 0);
> +
> + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask0);
Better (more logical nad consistent with other patches) spacing is like
this:
tcg_gen_mov_i64(cpu_gpr[rd], t1);
tcg_gen_movi_i64(t1, 0);
tcg_gen_andi_i64(t0, cpu_mmr[rt], mask0);
> + tcg_gen_shli_i64(t0, t0, 32);
> + tcg_gen_or_i64(t1, t0, t1);
> + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1);
> + tcg_gen_or_i64(t1, t0, t1);
> + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask2);
> + tcg_gen_shri_i64(t0, t0, 32);
> + tcg_gen_or_i64(t1, t0, t1);
> + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask3);
> + tcg_gen_or_i64(t1, t0, t1);
> +
> + tcg_gen_mov_i64(cpu_mmr[rd], t1);
> +
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + }
I think that if rt == rd this whole block can be rewritten in a more optimal
and clearer way:
tcg_gen_andi_i64(t0, cpu_gpr[rt], mask0);
tcg_gen_shli_i64(t0, t0, 32);
tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2);
tcg_gen_shri_i64(t1, t1, 32);
tcg_gen_andi_i64(cpu_gpr[rd], mask3 || mask1);
tcg_gen_or_i64(cpu_gpr[rd], t0);
tcg_gen_or_i64(cpu_gpr[rd], t1);
and the same for "mmr" half.
Aleksandar
> +}
> +
> #endif
>
>
> @@ -27670,7 +27741,6 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
> case MMI_OPC_2_PXOR: /* TODO: MMI_OPC_2_PXOR */
> case MMI_OPC_2_PMSUBH: /* TODO: MMI_OPC_2_PMSUBH */
> case MMI_OPC_2_PHMSBH: /* TODO: MMI_OPC_2_PHMSBH */
> - case MMI_OPC_2_PEXEH: /* TODO: MMI_OPC_2_PEXEH */
> case MMI_OPC_2_PREVH: /* TODO: MMI_OPC_2_PREVH */
> case MMI_OPC_2_PMULTH: /* TODO: MMI_OPC_2_PMULTH */
> case MMI_OPC_2_PDIVBW: /* TODO: MMI_OPC_2_PDIVBW */
> @@ -27681,6 +27751,9 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
> case MMI_OPC_2_PCPYLD:
> gen_mmi_pcpyld(ctx);
> break;
> + case MMI_OPC_2_PEXEH:
> + gen_mmi_pexeh(ctx);
> + break;
> default:
> MIPS_INVAL("TX79 MMI class MMI2");
> generate_exception_end(ctx, EXCP_RI);
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [Qemu-devel] [PATCH v3 06/13] target/mips: Add emulation of MMI instruction PEXEH
2019-03-04 18:27 ` Aleksandar Markovic
@ 2019-03-05 12:25 ` Richard Henderson
0 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2019-03-05 12:25 UTC (permalink / raw)
To: Aleksandar Markovic, Mateja Marjanovic, qemu-devel@nongnu.org
Cc: Aleksandar Rikalo, aurelien@aurel32.net
On 3/4/19 10:27 AM, Aleksandar Markovic wrote:
>> From: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
>> Subject: [PATCH v3 06/13] target/mips: Add emulation of MMI instruction PEXEH
>>
>> From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
>>
>> Add emulation of MMI instruction PEXEH. The emulation is implemented
>> using TCG front end operations directly to achieve better performance.
>>
>> Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
>> ---
>> target/mips/translate.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++++-
>> 1 file changed, 74 insertions(+), 1 deletion(-)
>>
>> diff --git a/target/mips/translate.c b/target/mips/translate.c
>> index 64eb10c..01efcde 100644
>> --- a/target/mips/translate.c
>> +++ b/target/mips/translate.c
>> @@ -24650,6 +24650,77 @@ static void gen_mmi_pexcw(DisasContext *ctx)
>> }
>> }
>>
>> +/*
>> + * PEXEH rd, rt
>> + *
>> + * Parallel Exchange Even Halfword
>
> Indentation...
>
>> + *
>> + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
>> + * +-----------+---------+---------+---------+---------+-----------+
>> + * | MMI |0 0 0 0 0| rt | rd | PEXEH | MMI2 |
>> + * +-----------+---------+---------+---------+---------+-----------+
>> + */
>> +
>> +static void gen_mmi_pexeh(DisasContext *ctx)
>> +{
>> + uint32_t pd, rt, rd;
>> + uint32_t opcode;
>> +
>> + opcode = ctx->opcode;
>> +
>> + pd = extract32(opcode, 21, 5);
>> + rt = extract32(opcode, 16, 5);
>> + rd = extract32(opcode, 11, 5);
>> +
>> + if (unlikely(pd != 0)) {
>> + generate_exception_end(ctx, EXCP_RI);
>> + } else if (rd == 0) {
>> + /* nop */
>> + } else if (rt == 0) {
>> + tcg_gen_movi_i64(cpu_gpr[rd], 0);
>> + tcg_gen_movi_i64(cpu_mmr[rd], 0);
>> + } else {
>> + TCGv_i64 t0 = tcg_temp_new();
>> + TCGv_i64 t1 = tcg_temp_new();
>> + uint64_t mask0 = (1ULL << 16) - 1;
>> + uint64_t mask1 = mask0 << 16;
>> + uint64_t mask2 = mask1 << 16;
>> + uint64_t mask3 = mask2 << 16;
>
> What about:
>
> uint64_t mask2 = mask0 << 32;
> uint64_t mask3 = mask0 << 48;
>
>> +
>> + tcg_gen_movi_i64(t1, 0);
>> +
>
> The last blank line should be deleted IMO.
>
>> + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask0);
>> + tcg_gen_shli_i64(t0, t0, 32);
>> + tcg_gen_or_i64(t1, t0, t1);
>> + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
>> + tcg_gen_or_i64(t1, t0, t1);
>> + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask2);
>> + tcg_gen_shri_i64(t0, t0, 32);
>> + tcg_gen_or_i64(t1, t0, t1);
>> + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask3);
>> + tcg_gen_or_i64(t1, t0, t1);
>> +
>> + tcg_gen_mov_i64(cpu_gpr[rd], t1);
>> + tcg_gen_movi_i64(t1, 0);
>> +
>> + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask0);
>
> Better (more logical nad consistent with other patches) spacing is like
> this:
>
> tcg_gen_mov_i64(cpu_gpr[rd], t1);
>
> tcg_gen_movi_i64(t1, 0);
> tcg_gen_andi_i64(t0, cpu_mmr[rt], mask0);
>
>> + tcg_gen_shli_i64(t0, t0, 32);
>> + tcg_gen_or_i64(t1, t0, t1);
>> + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1);
>> + tcg_gen_or_i64(t1, t0, t1);
>> + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask2);
>> + tcg_gen_shri_i64(t0, t0, 32);
>> + tcg_gen_or_i64(t1, t0, t1);
>> + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask3);
>> + tcg_gen_or_i64(t1, t0, t1);
>> +
>> + tcg_gen_mov_i64(cpu_mmr[rd], t1);
>> +
>> + tcg_temp_free(t0);
>> + tcg_temp_free(t1);
>> + }
>
> I think that if rt == rd this whole block can be rewritten in a more optimal
> and clearer way:
>
> tcg_gen_andi_i64(t0, cpu_gpr[rt], mask0);
> tcg_gen_shli_i64(t0, t0, 32);
> tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2);
> tcg_gen_shri_i64(t1, t1, 32);
>
> tcg_gen_andi_i64(cpu_gpr[rd], mask3 || mask1);
> tcg_gen_or_i64(cpu_gpr[rd], t0);
> tcg_gen_or_i64(cpu_gpr[rd], t1);
>
> and the same for "mmr" half.
You don't need rt == rd in order to write it that way:
tcg_gen_andi_i64(cpu_gpr[rd], cpu_gpr[rt], mask3 | mask1);
And yes, that's much better.
r~
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v3 07/13] target/mips: Add emulation of MMI instruction PEXEW
2019-03-04 15:13 [Qemu-devel] [PATCH v3 00/13] target/mips: Add emulation of data communication MMI instructions Mateja Marjanovic
` (5 preceding siblings ...)
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 06/13] target/mips: Add emulation of MMI instruction PEXEH Mateja Marjanovic
@ 2019-03-04 15:13 ` Mateja Marjanovic
2019-03-05 12:32 ` Richard Henderson
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 08/13] target/mips: Add emulation of MMI instruction PEXTLB Mateja Marjanovic
` (5 subsequent siblings)
12 siblings, 1 reply; 23+ messages in thread
From: Mateja Marjanovic @ 2019-03-04 15:13 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Add emulation of MMI instruction PEXEW. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/translate.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 64 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 01efcde..f55a0db 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24721,6 +24721,67 @@ static void gen_mmi_pexeh(DisasContext *ctx)
}
}
+/*
+ * PEXEW rd, rt
+ *
+ * Parallel Exchange Even Word
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI |0 0 0 0 0| rt | rd | PEXEW | MMI2 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+
+static void gen_mmi_pexew(DisasContext *ctx)
+{
+ uint32_t pd, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ pd = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (unlikely(pd != 0)) {
+ generate_exception_end(ctx, EXCP_RI);
+ } else if (rd == 0) {
+ /* nop */
+ } else if (rt == 0) {
+ tcg_gen_movi_i64(cpu_gpr[rd], 0);
+ tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ TCGv_i64 t2 = tcg_temp_new();
+ uint64_t mask0 = (1ULL << 32) - 1;
+ uint64_t mask1 = mask0 << 32;
+
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask0);
+ tcg_gen_shri_i64(t0, t0, 64);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_mov_i64(t2, t1);
+
+ tcg_gen_mov_i64(cpu_gpr[rd], t2);
+
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask0);
+ tcg_gen_shli_i64(t0, t0, 64);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1);
+ tcg_gen_or_i64(t1, t0, t1);
+
+ tcg_gen_mov_i64(cpu_mmr[rd], t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+ }
+}
+
#endif
@@ -27744,7 +27805,6 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_2_PREVH: /* TODO: MMI_OPC_2_PREVH */
case MMI_OPC_2_PMULTH: /* TODO: MMI_OPC_2_PMULTH */
case MMI_OPC_2_PDIVBW: /* TODO: MMI_OPC_2_PDIVBW */
- case MMI_OPC_2_PEXEW: /* TODO: MMI_OPC_2_PEXEW */
case MMI_OPC_2_PROT3W: /* TODO: MMI_OPC_2_PROT3W */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI2 */
break;
@@ -27754,6 +27814,9 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_2_PEXEH:
gen_mmi_pexeh(ctx);
break;
+ case MMI_OPC_2_PEXEW:
+ gen_mmi_pexew(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI2");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [Qemu-devel] [PATCH v3 07/13] target/mips: Add emulation of MMI instruction PEXEW
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 07/13] target/mips: Add emulation of MMI instruction PEXEW Mateja Marjanovic
@ 2019-03-05 12:32 ` Richard Henderson
0 siblings, 0 replies; 23+ messages in thread
From: Richard Henderson @ 2019-03-05 12:32 UTC (permalink / raw)
To: Mateja Marjanovic, qemu-devel; +Cc: arikalo, amarkovic, aurelien
On 3/4/19 7:13 AM, Mateja Marjanovic wrote:
> + } else {
> + TCGv_i64 t0 = tcg_temp_new();
> + TCGv_i64 t1 = tcg_temp_new();
> + TCGv_i64 t2 = tcg_temp_new();
> + uint64_t mask0 = (1ULL << 32) - 1;
> + uint64_t mask1 = mask0 << 32;
> +
> + tcg_gen_movi_i64(t1, 0);
> + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
> + tcg_gen_or_i64(t1, t0, t1);
> + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask0);
> + tcg_gen_shri_i64(t0, t0, 64);
This line should abort, since the shift count is out of range.
Are you testing with --enable-debug-tcg?
> + tcg_gen_or_i64(t1, t0, t1);
> + tcg_gen_mov_i64(t2, t1);
But again, this whole thing is two deposit operations:
tcg_gen_mov_i64(t0, cpu_gpr[rt]);
tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rt], cpu_mmr[rt], 0, 32);
tcg_gen_deposit_i64(cpu_mmr[rd], cpu_mmr[rt], t0, 0, 32);
r~
^ permalink raw reply [flat|nested] 23+ messages in thread
* [Qemu-devel] [PATCH v3 08/13] target/mips: Add emulation of MMI instruction PEXTLB
2019-03-04 15:13 [Qemu-devel] [PATCH v3 00/13] target/mips: Add emulation of data communication MMI instructions Mateja Marjanovic
` (6 preceding siblings ...)
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 07/13] target/mips: Add emulation of MMI instruction PEXEW Mateja Marjanovic
@ 2019-03-04 15:13 ` Mateja Marjanovic
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 09/13] target/mips: Add emulation of MMI instruction PEXTLH Mateja Marjanovic
` (4 subsequent siblings)
12 siblings, 0 replies; 23+ messages in thread
From: Mateja Marjanovic @ 2019-03-04 15:13 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Add emulation of MMI instruction PEXTLB. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/translate.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 95 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f55a0db..e84262f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24782,6 +24782,98 @@ static void gen_mmi_pexew(DisasContext *ctx)
}
}
+/*
+ * PEXTLB rd, rs, rt
+ *
+ * Parallel Extend Lower from Byte
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI | rs | rt | rd | PEXTLB | MMI0 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+
+static void gen_mmi_pextlb(DisasContext *ctx)
+{
+ uint32_t rs, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ rs = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (rd == 0) {
+ /* nop */
+ } else {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask = ((1ULL << 8) - 1) << 56;
+
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_shri_i64(t0, t0, 8);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask >>= 8;
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_shri_i64(t0, t0, 8);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask >>= 8;
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_shri_i64(t0, t0, 8);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask >>= 8;
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_shri_i64(t0, t0, 8);
+ tcg_gen_or_i64(t1, t0, t1);
+
+ tcg_gen_mov_i64(cpu_mmr[rd], t1);
+
+ mask >>= 8;
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_shri_i64(t0, t0, 8);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask >>= 8;
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_shri_i64(t0, t0, 8);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask >>= 8;
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_shri_i64(t0, t0, 8);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask >>= 8;
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_shri_i64(t0, t0, 8);
+ tcg_gen_or_i64(t1, t0, t1);
+
+ tcg_gen_mov_i64(cpu_gpr[rd], t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+}
+
#endif
@@ -27737,12 +27829,14 @@ static void decode_mmi0(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_0_PPACH: /* TODO: MMI_OPC_0_PPACH */
case MMI_OPC_0_PADDSB: /* TODO: MMI_OPC_0_PADDSB */
case MMI_OPC_0_PSUBSB: /* TODO: MMI_OPC_0_PSUBSB */
- case MMI_OPC_0_PEXTLB: /* TODO: MMI_OPC_0_PEXTLB */
case MMI_OPC_0_PPACB: /* TODO: MMI_OPC_0_PPACB */
case MMI_OPC_0_PEXT5: /* TODO: MMI_OPC_0_PEXT5 */
case MMI_OPC_0_PPAC5: /* TODO: MMI_OPC_0_PPAC5 */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI0 */
break;
+ case MMI_OPC_0_PEXTLB:
+ gen_mmi_pextlb(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI0");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [Qemu-devel] [PATCH v3 09/13] target/mips: Add emulation of MMI instruction PEXTLH
2019-03-04 15:13 [Qemu-devel] [PATCH v3 00/13] target/mips: Add emulation of data communication MMI instructions Mateja Marjanovic
` (7 preceding siblings ...)
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 08/13] target/mips: Add emulation of MMI instruction PEXTLB Mateja Marjanovic
@ 2019-03-04 15:13 ` Mateja Marjanovic
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 10/13] target/mips: Add emulation of MMI instruction PEXTLW Mateja Marjanovic
` (3 subsequent siblings)
12 siblings, 0 replies; 23+ messages in thread
From: Mateja Marjanovic @ 2019-03-04 15:13 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Add emulation of MMI instruction PEXTLH. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/translate.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 69 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e84262f..5c2fc07 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24874,6 +24874,72 @@ static void gen_mmi_pextlb(DisasContext *ctx)
}
}
+/*
+ * PEXTLH rd, rs, rt
+ *
+ * Parallel Extend Lower from Halfword
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI | rs | rt | rd | PEXTLH | MMI0 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+
+static void gen_mmi_pextlh(DisasContext *ctx)
+{
+ uint32_t rs, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ rs = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (rd == 0) {
+ /* nop */
+ } else {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask = ((1ULL << 16) - 1) << 48;
+
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_shri_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask >>= 16;
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_shri_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+
+ tcg_gen_mov_i64(cpu_mmr[rd], t1);
+
+ mask >>= 16;
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_shri_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask >>= 16;
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_shri_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask >>= 16;
+
+ tcg_gen_mov_i64(cpu_gpr[rd], t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+}
+
#endif
@@ -27825,7 +27891,6 @@ static void decode_mmi0(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_0_PPACW: /* TODO: MMI_OPC_0_PPACW */
case MMI_OPC_0_PADDSH: /* TODO: MMI_OPC_0_PADDSH */
case MMI_OPC_0_PSUBSH: /* TODO: MMI_OPC_0_PSUBSH */
- case MMI_OPC_0_PEXTLH: /* TODO: MMI_OPC_0_PEXTLH */
case MMI_OPC_0_PPACH: /* TODO: MMI_OPC_0_PPACH */
case MMI_OPC_0_PADDSB: /* TODO: MMI_OPC_0_PADDSB */
case MMI_OPC_0_PSUBSB: /* TODO: MMI_OPC_0_PSUBSB */
@@ -27837,6 +27902,9 @@ static void decode_mmi0(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_0_PEXTLB:
gen_mmi_pextlb(ctx);
break;
+ case MMI_OPC_0_PEXTLH:
+ gen_mmi_pextlh(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI0");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [Qemu-devel] [PATCH v3 10/13] target/mips: Add emulation of MMI instruction PEXTLW
2019-03-04 15:13 [Qemu-devel] [PATCH v3 00/13] target/mips: Add emulation of data communication MMI instructions Mateja Marjanovic
` (8 preceding siblings ...)
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 09/13] target/mips: Add emulation of MMI instruction PEXTLH Mateja Marjanovic
@ 2019-03-04 15:13 ` Mateja Marjanovic
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 11/13] target/mips: Add emulation of MMI instruction PEXTUB Mateja Marjanovic
` (2 subsequent siblings)
12 siblings, 0 replies; 23+ messages in thread
From: Mateja Marjanovic @ 2019-03-04 15:13 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Add emulation of MMI instruction PEXTLW. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/translate.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 5c2fc07..e08203f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24940,6 +24940,59 @@ static void gen_mmi_pextlh(DisasContext *ctx)
}
}
+/*
+ * PEXTLW rd, rs, rt
+ *
+ * Parallel Extend Lower from Word
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI | rs | rt | rd | PEXTLW | MMI0 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+
+static void gen_mmi_pextlw(DisasContext *ctx)
+{
+ uint32_t rs, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ rs = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (rd == 0) {
+ /* nop */
+ } else {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask = ((1ULL << 32) - 1) << 32;
+
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_shri_i64(t0, t0, 32);
+ tcg_gen_or_i64(t1, t0, t1);
+
+ tcg_gen_mov_i64(cpu_mmr[rd], t1);
+
+ mask >>= 32;
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_shri_i64(t0, t0, 32);
+ tcg_gen_or_i64(t1, t0, t1);
+
+ tcg_gen_mov_i64(cpu_gpr[rd], t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+}
+
#endif
@@ -27887,7 +27940,6 @@ static void decode_mmi0(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_0_PCGTB: /* TODO: MMI_OPC_0_PCGTB */
case MMI_OPC_0_PADDSW: /* TODO: MMI_OPC_0_PADDSW */
case MMI_OPC_0_PSUBSW: /* TODO: MMI_OPC_0_PSUBSW */
- case MMI_OPC_0_PEXTLW: /* TODO: MMI_OPC_0_PEXTLW */
case MMI_OPC_0_PPACW: /* TODO: MMI_OPC_0_PPACW */
case MMI_OPC_0_PADDSH: /* TODO: MMI_OPC_0_PADDSH */
case MMI_OPC_0_PSUBSH: /* TODO: MMI_OPC_0_PSUBSH */
@@ -27905,6 +27957,9 @@ static void decode_mmi0(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_0_PEXTLH:
gen_mmi_pextlh(ctx);
break;
+ case MMI_OPC_0_PEXTLW:
+ gen_mmi_pextlw(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI0");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [Qemu-devel] [PATCH v3 11/13] target/mips: Add emulation of MMI instruction PEXTUB
2019-03-04 15:13 [Qemu-devel] [PATCH v3 00/13] target/mips: Add emulation of data communication MMI instructions Mateja Marjanovic
` (9 preceding siblings ...)
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 10/13] target/mips: Add emulation of MMI instruction PEXTLW Mateja Marjanovic
@ 2019-03-04 15:13 ` Mateja Marjanovic
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 12/13] target/mips: Add emulation of MMI instruction PEXTUH Mateja Marjanovic
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 13/13] target/mips: Add emulation of MMI instruction PEXTUW Mateja Marjanovic
12 siblings, 0 replies; 23+ messages in thread
From: Mateja Marjanovic @ 2019-03-04 15:13 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Add emulation of MMI instruction PEXTUB. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/translate.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 95 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e08203f..1bd5ef2 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24993,6 +24993,98 @@ static void gen_mmi_pextlw(DisasContext *ctx)
}
}
+/*
+ * PEXTUB rd, rs, rt
+ *
+ * Parallel Extend Upper from Byte
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI | rs | rt | rd | PEXTUB | MMI1 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+
+static void gen_mmi_pextub(DisasContext *ctx)
+{
+ uint32_t rs, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ rs = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (rd == 0) {
+ /* nop */
+ } else {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask = (1ULL << 8) - 1;
+
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_shli_i64(t0, t0, 8);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask <<= 8;
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_shli_i64(t0, t0, 8);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask <<= 8;
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_shli_i64(t0, t0, 8);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask <<= 8;
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_shli_i64(t0, t0, 8);
+ tcg_gen_or_i64(t1, t0, t1);
+
+ tcg_gen_mov_i64(cpu_mmr[rd], t1);
+
+ mask <<= 8;
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_shli_i64(t0, t0, 8);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask <<= 8;
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_shli_i64(t0, t0, 8);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask <<= 8;
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_shli_i64(t0, t0, 8);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask <<= 8;
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_shli_i64(t0, t0, 8);
+ tcg_gen_or_i64(t1, t0, t1);
+
+ tcg_gen_mov_i64(cpu_gpr[rd], t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+}
+
#endif
@@ -27988,10 +28080,12 @@ static void decode_mmi1(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_1_PEXTUH: /* TODO: MMI_OPC_1_PEXTUH */
case MMI_OPC_1_PADDUB: /* TODO: MMI_OPC_1_PADDUB */
case MMI_OPC_1_PSUBUB: /* TODO: MMI_OPC_1_PSUBUB */
- case MMI_OPC_1_PEXTUB: /* TODO: MMI_OPC_1_PEXTUB */
case MMI_OPC_1_QFSRV: /* TODO: MMI_OPC_1_QFSRV */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI1 */
break;
+ case MMI_OPC_1_PEXTUB:
+ gen_mmi_pextub(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI1");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [Qemu-devel] [PATCH v3 12/13] target/mips: Add emulation of MMI instruction PEXTUH
2019-03-04 15:13 [Qemu-devel] [PATCH v3 00/13] target/mips: Add emulation of data communication MMI instructions Mateja Marjanovic
` (10 preceding siblings ...)
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 11/13] target/mips: Add emulation of MMI instruction PEXTUB Mateja Marjanovic
@ 2019-03-04 15:13 ` Mateja Marjanovic
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 13/13] target/mips: Add emulation of MMI instruction PEXTUW Mateja Marjanovic
12 siblings, 0 replies; 23+ messages in thread
From: Mateja Marjanovic @ 2019-03-04 15:13 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Add emulation of MMI instruction PEXTUH. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/translate.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 69 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1bd5ef2..da3fcad 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -25085,6 +25085,72 @@ static void gen_mmi_pextub(DisasContext *ctx)
}
}
+/*
+ * PEXTUH rd, rs, rt
+ *
+ * Parallel Extend Upper from Halfword
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI | rs | rt | rd | PEXTUH | MMI1 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+
+static void gen_mmi_pextuh(DisasContext *ctx)
+{
+ uint32_t rs, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ rs = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (rd == 0) {
+ /* nop */
+ } else {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask = (1ULL << 16) - 1;
+
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask <<= 16;
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask <<= 16;
+
+ tcg_gen_mov_i64(cpu_mmr[rd], t1);
+ tcg_gen_movi_i64(t1, 0);
+
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask <<= 16;
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask <<= 16;
+
+ tcg_gen_mov_i64(cpu_gpr[rd], t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+}
+
#endif
@@ -28077,7 +28143,6 @@ static void decode_mmi1(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_1_PEXTUW: /* TODO: MMI_OPC_1_PEXTUW */
case MMI_OPC_1_PADDUH: /* TODO: MMI_OPC_1_PADDUH */
case MMI_OPC_1_PSUBUH: /* TODO: MMI_OPC_1_PSUBUH */
- case MMI_OPC_1_PEXTUH: /* TODO: MMI_OPC_1_PEXTUH */
case MMI_OPC_1_PADDUB: /* TODO: MMI_OPC_1_PADDUB */
case MMI_OPC_1_PSUBUB: /* TODO: MMI_OPC_1_PSUBUB */
case MMI_OPC_1_QFSRV: /* TODO: MMI_OPC_1_QFSRV */
@@ -28086,6 +28151,9 @@ static void decode_mmi1(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_1_PEXTUB:
gen_mmi_pextub(ctx);
break;
+ case MMI_OPC_1_PEXTUH:
+ gen_mmi_pextuh(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI1");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread* [Qemu-devel] [PATCH v3 13/13] target/mips: Add emulation of MMI instruction PEXTUW
2019-03-04 15:13 [Qemu-devel] [PATCH v3 00/13] target/mips: Add emulation of data communication MMI instructions Mateja Marjanovic
` (11 preceding siblings ...)
2019-03-04 15:13 ` [Qemu-devel] [PATCH v3 12/13] target/mips: Add emulation of MMI instruction PEXTUH Mateja Marjanovic
@ 2019-03-04 15:13 ` Mateja Marjanovic
12 siblings, 0 replies; 23+ messages in thread
From: Mateja Marjanovic @ 2019-03-04 15:13 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Add emulation of MMI instruction PEXTUW. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/translate.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 57 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index da3fcad..5848f7a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -25151,6 +25151,60 @@ static void gen_mmi_pextuh(DisasContext *ctx)
}
}
+/*
+ * PEXTUW rd, rs, rt
+ *
+ * Parallel Extend Upper from Word
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI | rs | rt | rd | PEXTUW | MMI1 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+
+static void gen_mmi_pextuw(DisasContext *ctx)
+{
+ uint32_t rs, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ rs = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (rd == 0) {
+ /* nop */
+ } else {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask = (1ULL << 32) - 1;
+
+ tcg_gen_movi_i64(t1, 0);
+
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_shli_i64(t0, t0, 32);
+ tcg_gen_or_i64(t1, t0, t1);
+ mask <<= 32;
+
+ tcg_gen_mov_i64(cpu_mmr[rd], t1);
+ tcg_gen_movi_i64(t1, 0);
+
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_andi_i64(t0, cpu_gpr[rs], mask);
+ tcg_gen_shli_i64(t0, t0, 32);
+ tcg_gen_or_i64(t1, t0, t1);
+
+ tcg_gen_mov_i64(cpu_gpr[rd], t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+}
+
#endif
@@ -28140,7 +28194,6 @@ static void decode_mmi1(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_1_PCEQB: /* TODO: MMI_OPC_1_PCEQB */
case MMI_OPC_1_PADDUW: /* TODO: MMI_OPC_1_PADDUW */
case MMI_OPC_1_PSUBUW: /* TODO: MMI_OPC_1_PSUBUW */
- case MMI_OPC_1_PEXTUW: /* TODO: MMI_OPC_1_PEXTUW */
case MMI_OPC_1_PADDUH: /* TODO: MMI_OPC_1_PADDUH */
case MMI_OPC_1_PSUBUH: /* TODO: MMI_OPC_1_PSUBUH */
case MMI_OPC_1_PADDUB: /* TODO: MMI_OPC_1_PADDUB */
@@ -28154,6 +28207,9 @@ static void decode_mmi1(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_1_PEXTUH:
gen_mmi_pextuh(ctx);
break;
+ case MMI_OPC_1_PEXTUW:
+ gen_mmi_pextuw(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI1");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 23+ messages in thread