From: Richard Henderson <richard.henderson@linaro.org>
To: Laurent Vivier <lvivier@redhat.com>, qemu-devel@nongnu.org
Cc: Richard Henderson <rth@twiddle.net>
Subject: Re: [Qemu-devel] [PATCH v3] tcg: workaround branch instruction overflow in tcg_out_qemu_ld/st
Date: Tue, 1 May 2018 11:43:21 -0700 [thread overview]
Message-ID: <46927e99-c504-fd3f-cc8e-98f08ef75efb@linaro.org> (raw)
In-Reply-To: <20180429235840.16659-1-lvivier@redhat.com>
On 04/29/2018 04:58 PM, Laurent Vivier wrote:
> ppc64 uses a BC instruction to call the tcg_out_qemu_ld/st
> slow path. BC instruction uses a relative address encoded
> on 14 bits.
>
> The slow path functions are added at the end of the generated
> instructions buffer, in the reverse order of the callers.
> So more we have slow path functions more the distance between
> the caller (BC) and the function increases.
>
> This patch changes the behavior to generate the functions in
> the same order of the callers.
>
> Fixes: 15fa08f845 ("tcg: Dynamically allocate TCGOps")
> Signed-off-by: Laurent Vivier <lvivier@redhat.com>
> ---
Thanks, applied to tcg-next.
r~
prev parent reply other threads:[~2018-05-01 18:43 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-29 23:58 [Qemu-devel] [PATCH v3] tcg: workaround branch instruction overflow in tcg_out_qemu_ld/st Laurent Vivier
2018-05-01 18:43 ` Richard Henderson [this message]
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