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Date: Wed, 26 Sep 2007 11:47:10 +0200
From: Fabrice Bellard <fabrice@bellard.org>
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Subject: Re: [Qemu-devel] [PATCH][MIPS] Fix [ls][wd][lr] instructions
References: <20070926092330.GA29659@hall.aurel32.net>
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To: qemu-devel@nongnu.org

Aurelien Jarno wrote:
> Hi,
> 
> As written in the MIPS TODO file, the lwl, lwr, ldl, ldr, swl, swr,
> sdl and sdr instructions are not correctly implemented. In case of 
> exception the BadVAddr register gets the aligned address instead of the
> unaligned original address.
> 
> In addition to that, the store instructions are generating the wrong
> exception, AdEl instead of AdEs, because the current implementation 
> first do a load.
> 
> The patch below fixes that by accessing the bytes one by one, starting
> by the unaligned original address.
> 
> Bye,
> Aurelien

[...]

BTW, you could simplify a lot the implementation :

     switch (GET_LMASK(T0)) {
     case 0:
         T0 = (int32_t)tmp;
         break;
     case 1:
         T0 = (int32_t)((tmp << 8) | (T1 & 0x000000FF));
         break;
     case 2:
         T0 = (int32_t)((tmp << 16) | (T1 & 0x0000FFFF));
         break;
     case 3:
         T0 = (int32_t)((tmp << 24) | (T1 & 0x00FFFFFF));
         break;
     }

->

v = GET_LMASK(T0);
if (v == 0) {
	T0 = tmp;
} else {
	TO = (int32_t)((tmp << (8 * v)) | (T1 & ((1 << (v * 8)) - 1)));
}

Fabrice.