From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1IaUPB-00054b-R2 for qemu-devel@nongnu.org; Wed, 26 Sep 2007 06:46:09 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1IaUPA-000545-KH for qemu-devel@nongnu.org; Wed, 26 Sep 2007 06:46:08 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1IaUPA-00053q-CU for qemu-devel@nongnu.org; Wed, 26 Sep 2007 06:46:08 -0400 Received: from hall.aurel32.net ([88.191.38.19]) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1IaUPA-0003qW-3E for qemu-devel@nongnu.org; Wed, 26 Sep 2007 06:46:08 -0400 Received: from [91.84.211.115] (helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.63) (envelope-from ) id 1IaUP6-0000AW-42 for qemu-devel@nongnu.org; Wed, 26 Sep 2007 12:46:04 +0200 Received: from localhost.aurel32.net ([127.0.0.1] ident=aurel32) by volta.aurel32.net with esmtp (Exim 4.67) (envelope-from ) id 1IaUOq-0006dx-Rf for qemu-devel@nongnu.org; Wed, 26 Sep 2007 12:45:48 +0200 Message-ID: <46FA385C.50505@aurel32.net> Date: Wed, 26 Sep 2007 12:45:48 +0200 From: Aurelien Jarno MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH][MIPS] Fix [ls][wd][lr] instructions References: <20070926092330.GA29659@hall.aurel32.net> <46FA2BE1.3070307@bellard.org> In-Reply-To: <46FA2BE1.3070307@bellard.org> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Fabrice Bellard a écrit : > Aurelien Jarno wrote: >> Hi, >> >> As written in the MIPS TODO file, the lwl, lwr, ldl, ldr, swl, swr, >> sdl and sdr instructions are not correctly implemented. In case of >> exception the BadVAddr register gets the aligned address instead of the >> unaligned original address. >> >> In addition to that, the store instructions are generating the wrong >> exception, AdEl instead of AdEs, because the current implementation >> first do a load. >> >> The patch below fixes that by accessing the bytes one by one, starting >> by the unaligned original address. > > [...] > > It would be a lot more efficient to add specific code in the MIPS > exception handling. > That was the first approach I tried to follow, but it is not that easy. Basically the solution is to add a new flag to CPUMIPSState to mark instructions that need fix when an exception occurs and then fix the exception type and address if needed. Given those instructions are not used that often (unaligned memory accesses have to be avoided), I am not sure it is worth adding too much complexity in the mmu fault and exception handling code, which is used by all instructions. -- .''`. Aurelien Jarno | GPG: 1024D/F1BCDB73 : :' : Debian developer | Electrical Engineer `. `' aurel32@debian.org | aurelien@aurel32.net `- people.debian.org/~aurel32 | www.aurel32.net