From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:34284) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hMOv4-0006zk-Qj for qemu-devel@nongnu.org; Thu, 02 May 2019 23:31:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hMOv3-00045H-NV for qemu-devel@nongnu.org; Thu, 02 May 2019 23:31:30 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:36457) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hMOv3-00044x-HL for qemu-devel@nongnu.org; Thu, 02 May 2019 23:31:29 -0400 Received: by mail-pl1-x644.google.com with SMTP id w20so2024912plq.3 for ; Thu, 02 May 2019 20:31:28 -0700 (PDT) References: <20190503002206.9751-1-driver1998@foxmail.com> <20190503003707.10185-1-driver1998@foxmail.com> From: Richard Henderson Message-ID: <46c2245c-3133-8335-226d-007b6e22c2f4@linaro.org> Date: Thu, 2 May 2019 20:31:23 -0700 MIME-Version: 1.0 In-Reply-To: <20190503003707.10185-1-driver1998@foxmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3 3/4] util/cacheinfo: Use uint64_t on LLP64 model to satisfy Windows ARM64 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Cao Jiaxi , qemu-devel@nongnu.org On 5/2/19 5:37 PM, Cao Jiaxi wrote: > Windows ARM64 uses LLP64 model, which breaks current assumptions. > > Signed-off-by: Cao Jiaxi > --- > util/cacheinfo.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/util/cacheinfo.c b/util/cacheinfo.c > index 3cd080b83d..eebe1ce9c5 100644 > --- a/util/cacheinfo.c > +++ b/util/cacheinfo.c > @@ -107,7 +107,7 @@ static void sys_cache_info(int *isize, int *dsize) > static void arch_cache_info(int *isize, int *dsize) > { > if (*isize == 0 || *dsize == 0) { > - unsigned long ctr; > + uint64_t ctr; > > /* The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1, > but (at least under Linux) these are marked protected by the > Reviewed-by: Richard Henderson r~ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC1CAC43219 for ; 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[97.113.189.189]) by smtp.gmail.com with ESMTPSA id i3sm798951pfa.90.2019.05.02.20.31.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 02 May 2019 20:31:25 -0700 (PDT) To: Cao Jiaxi , qemu-devel@nongnu.org References: <20190503002206.9751-1-driver1998@foxmail.com> <20190503003707.10185-1-driver1998@foxmail.com> From: Richard Henderson Openpgp: preference=signencrypt Message-ID: <46c2245c-3133-8335-226d-007b6e22c2f4@linaro.org> Date: Thu, 2 May 2019 20:31:23 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190503003707.10185-1-driver1998@foxmail.com> Content-Type: text/plain; charset="UTF-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: Re: [Qemu-devel] [PATCH v3 3/4] util/cacheinfo: Use uint64_t on LLP64 model to satisfy Windows ARM64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Message-ID: <20190503033123.SUAKDTGmb2mXml6Sgm37QgWx60KqCnyRpahtvBIxumk@z> On 5/2/19 5:37 PM, Cao Jiaxi wrote: > Windows ARM64 uses LLP64 model, which breaks current assumptions. > > Signed-off-by: Cao Jiaxi > --- > util/cacheinfo.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/util/cacheinfo.c b/util/cacheinfo.c > index 3cd080b83d..eebe1ce9c5 100644 > --- a/util/cacheinfo.c > +++ b/util/cacheinfo.c > @@ -107,7 +107,7 @@ static void sys_cache_info(int *isize, int *dsize) > static void arch_cache_info(int *isize, int *dsize) > { > if (*isize == 0 || *dsize == 0) { > - unsigned long ctr; > + uint64_t ctr; > > /* The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1, > but (at least under Linux) these are marked protected by the > Reviewed-by: Richard Henderson r~