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Mon, 05 Feb 2024 05:20:26 -0800 (PST) Message-ID: <46d14718-2b2c-45aa-aa12-854a2704383b@linaro.org> Date: Mon, 5 Feb 2024 14:20:25 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v0 2/2] aspeed: fix hardcode boot address 0 Content-Language: en-US To: Jamin Lin , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" Cc: troy_lee@aspeedtech.com References: <20240205091415.935686-1-jamin_lin@aspeedtech.com> <20240205091415.935686-3-jamin_lin@aspeedtech.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240205091415.935686-3-jamin_lin@aspeedtech.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Jamin, On 5/2/24 10:14, Jamin Lin via wrote: > In the previous design of QEMU model for ASPEED SOCs, it set the boot > address at 0 which was the hardcode setting for ast10x0, ast2600, > ast2500 and ast2400. > > According to the design of ast2700, it has bootmcu which is used for > executing SPL and initialize DRAM, Out of curiosity, what architecture is this MCU? > then, CPUs(cortex-a35) > execute u-boot, kernel and rofs. QEMU will only support CPU(coretax-a35) > parts and the boot address is "0x400000000" for ast2700. OK, but I don't get how you get from here ... > Therefore, fixed hardcode boot address 0. ... to here. > Signed-off-by: Troy Lee > Signed-off-by: Jamin Lin > --- > hw/arm/aspeed.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > index 218b81298e..82a92e8142 100644 > --- a/hw/arm/aspeed.c > +++ b/hw/arm/aspeed.c > @@ -289,12 +289,14 @@ static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk, > uint64_t rom_size) > { > AspeedSoCState *soc = bmc->soc; > + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc); > > memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_size, > &error_abort); > memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, > &bmc->boot_rom, 1); > - write_boot_rom(blk, ASPEED_SOC_SPI_BOOT_ADDR, rom_size, &error_abort); > + write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT], > + rom_size, &error_abort); Reviewed-by: Philippe Mathieu-Daudé > } > > void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,