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From: Richard Henderson <richard.henderson@linaro.org>
To: Rebecca Cran <rebecca@nuviainc.com>, qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>
Subject: Re: [PATCH 1/2] target/arm: add support for FEAT_DIT, Data Independent Timing
Date: Fri, 11 Dec 2020 13:51:40 -0600	[thread overview]
Message-ID: <46d7b991-d305-bd2f-91f9-cdc2ee1e73ce@linaro.org> (raw)
In-Reply-To: <284b9f4e-55b7-81a3-f1c5-7f7b6d0c9784@nuviainc.com>

On 12/11/20 1:33 PM, Rebecca Cran wrote:
> Is the comment in target/arm/op_helper.c:397 still relevant?
> 
> uint32_t HELPER(cpsr_read)(CPUARMState *env)
> {
>     /*
>      * We store the ARMv8 PSTATE.SS bit in env->uncached_cpsr.
>      * This is convenient for populating SPSR_ELx, but must be
>      * hidden from aarch32 mode, where it is not visible.
>      *
>      * TODO: ARMv8.4-DIT -- need to move SS somewhere else.
>      */
>     return cpsr_read(env) & ~(CPSR_EXEC | PSTATE_SS);
> }

I forgot about this.  So we can't "just" store DIT in uncached_cpsr.

I'll let Peter weigh in, but I think it makes sense to move the SS bit
somewhere else (e.g. env->pstate) and merge it into SPSR_ELx upon interrupt.
While what we're doing here is convenient, it's not architectural, and it would
be better to follow GetPSRFromPSTATE pseudocode.


r~


  reply	other threads:[~2020-12-11 19:59 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-11  5:13 [PATCH 0/2] target/arm: Add support for DIT (Data Independent Timing) Rebecca Cran
2020-12-11  5:13 ` [PATCH 1/2] target/arm: add support for FEAT_DIT, Data Independent Timing Rebecca Cran
2020-12-11 14:08   ` Richard Henderson
2020-12-11 19:33     ` Rebecca Cran
2020-12-11 19:51       ` Richard Henderson [this message]
2020-12-11 21:37         ` Peter Maydell
2020-12-14 18:11           ` Rebecca Cran
2020-12-14 18:48             ` Peter Maydell
2020-12-11  5:13 ` [PATCH 2/2] target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU Rebecca Cran
2020-12-11 14:09   ` Richard Henderson

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