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[92.88.170.6]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38f258dcc45sm1848611f8f.33.2025.02.13.04.59.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 13 Feb 2025 04:59:19 -0800 (PST) Message-ID: <46ffafd4-111c-4583-9039-da61d6a9cd80@linaro.org> Date: Thu, 13 Feb 2025 13:59:18 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/9] target/microblaze: Split out mb_transaction_failed_internal To: Richard Henderson , qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com References: <20250212220155.1147144-1-richard.henderson@linaro.org> <20250212220155.1147144-3-richard.henderson@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250212220155.1147144-3-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/2/25 23:01, Richard Henderson wrote: > Use an explicit 64-bit type for the address to store in EAR. > > Signed-off-by: Richard Henderson > --- > target/microblaze/op_helper.c | 70 +++++++++++++++++++++-------------- > 1 file changed, 42 insertions(+), 28 deletions(-) > +static void mb_transaction_failed_internal(CPUState *cs, hwaddr physaddr, > + uint64_t addr, unsigned size, > + MMUAccessType access_type, > + uintptr_t retaddr) > +{ > + CPUMBState *env = cpu_env(cs); > + MicroBlazeCPU *cpu = env_archcpu(env); > + const char *access_name = "INVALID"; > + bool take = env->msr & MSR_EE; > + uint32_t esr = ESR_EC_DATA_BUS; > + > + switch (access_type) { > + case MMU_INST_FETCH: > + access_name = "INST_FETCH"; > + esr = ESR_EC_INSN_BUS; > + take &= cpu->cfg.iopb_bus_exception; > + break; > + case MMU_DATA_LOAD: > + access_name = "DATA_LOAD"; > + take &= cpu->cfg.dopb_bus_exception; > + break; > + case MMU_DATA_STORE: > + access_name = "DATA_STORE"; > + take &= cpu->cfg.dopb_bus_exception; > + break; > + } > + > + qemu_log_mask(CPU_LOG_INT, "Transaction failed: addr 0x%" PRIx64 > + "physaddr 0x" HWADDR_FMT_plx " size %d access-type %s (%s)\n", > + addr, physaddr, size, access_name, > + take ? "TAKEN" : "DROPPED"); Helpful. Reviewed-by: Philippe Mathieu-Daudé > + > + if (take) { > + env->esr = esr; > + env->ear = addr; > + cs->exception_index = EXCP_HW_EXCP; > + cpu_loop_exit_restore(cs, retaddr); > + } > +}