Re: [Qemu-devel] U-Boot patch for qemu -M mips

[Vlad Lungu <vlad@comsys.ro>]

Thiemo Seufer wrote:
> Vlad Lungu wrote:
>   
>>  Fix for mips GOT relocation bug, NE2000 bugs, add support for qemu -M mips target.
>>     
> [snip]
>   
>>  diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk
>>     
[snip]
>>  +#
>>  +# AMD development board AMD Alchemy DbAu1x00, MIPS32 core
>>     
>
> Incorrect comment.
>
>   
didn't spot that
>>  +#
>>  +
>>  +# ROM version
>>  +TEXT_BASE = 0xbfc00000
>>  +
>>  +# RAM version
>>  +#TEXT_BASE = 0x80100000
>>     
>
> This could be as low as 0x80001000 (assuming the space for exception
> handlers isn't reserved by other means).
>   
I think I saw that difference in Linux 2.6 too. I suppose you're right.
> [snip]
>   
>>  diff --git a/board/qemu-mips/lowlevel_init.S b/board/qemu-mips/lowlevel_init.S
>>  new file mode 100644
>>  index 0000000..855e8ab
>>  --- /dev/null
>>  +++ b/board/qemu-mips/lowlevel_init.S
>>  @@ -0,0 +1,47 @@
>>  +/* Memory sub-system initialization code */
>>  +
>>  +#include <config.h>
>>  +#include <version.h>
>>  +#include <asm/regdef.h>
>>  +#include <asm/mipsregs.h>
>>  +
>>  +       .text
>>  +       .set noreorder
>>  +       .set mips32
>>  +
>>  +       .globl  lowlevel_init
>>  +lowlevel_init:
>>  +
>>  +       /*
>>  +        * Step 2) Establish Status Register
>>  +        * (set BEV, clear ERL, clear EXL, clear IE)
>>  +        */
>>  +       li      t1, 0x00400000
>>  +       mtc0    t1, CP0_STATUS
>>  +
>>  +       /*
>>  +        * Step 3) Establish CP0 Config0
>>  +        * (set OD, set K0=3)
>>  +        */
>>  +       li      t1, 0x00080003
>>  +       mtc0    t1, CP0_CONFIG
>>     
>
> OD is a processor-specific flag, it does nothing on Qemu.
>
>   
>>  +       /*
>>  +        * Step 5) Disable the performance counters
>>  +        */
>>  +       mtc0    zero, CP0_PERFORMANCE
>>  +       nop
>>     
>
> This field isn't required to exist (as per architecture spec), which
> means you can get an exception when writing it. Since perfctr
> interrupts are guaranteed to be disabled, the best option is not to
> touch the register in early startup code.
>
> (If you want to use performance counters, first check via the config
> registers if they are implemented. You won't have much luck on Qemu:
> The registers are implemented, but they don't do anything useful.)
>   
Well, I didn't get any exception . And nobody complained about OD 
either. The stuff that barfed on me, I deleted right away.
I'll delete this too, no problem.
>>  +       /*
>>  +        * Step 7) Establish Cause
>>  +        * (set IV bit)
>>  +        */
>>  +       li      t1, 0x00800000
>>  +       mtc0    t1, CP0_CAUSE
>>  +
>>  +       /* Establish Wired (and Random) */
>>  +       mtc0    zero, CP0_WIRED
>>  +       nop
>>  +
>>  +       j       ra
>>  +       nop
>>  diff --git a/board/qemu-mips/qemu-mips.c b/board/qemu-mips/qemu-mips.c
>>  new file mode 100644
>>  index 0000000..76c093c
>>  --- /dev/null
>>  +++ b/board/qemu-mips/qemu-mips.c
>>  @@ -0,0 +1,48 @@
>>  +/*
>>  + * (C) Copyright 2007
>>  + * [5]vlad@comsys.ro
>>     
>
> A name in addition would look nicer. :-)
>
>   
Names are so passe :-)
>>  + *
>>  + * See file CREDITS for list of people who contributed to this
>>  + * project.
>>  + *
>>  + * This program is free software; you can redistribute it and/or
>>  + * modify it under the terms of the GNU General Public License as
>>  + * published by the Free Software Foundation; either version 2 of
>>  + * the License, or (at your option) any later version.
>>  + *
>>  + * This program is distributed in the hope that it will be useful,
>>  + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>  + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>  + * GNU General Public License for more details.
>>  + *
>>  + * You should have received a copy of the GNU General Public License
>>  + * along with this program; if not, write to the Free Software
>>  + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>>  + * MA 02111-1307 USA
>>  + */
>>  +
>>  +#include <common.h>
>>  +#include <command.h>
>>  +#include <asm/mipsregs.h>
>>  +
>>  +long int initdram(int board_type)
>>  +{
>>  +       /* Sdram is setup by assembler code */
>>  +       /* If memory could be changed, we should return the true value here */
>>  +       return MEM_SIZE*1024*1024;
>>     
>
> Qemu gets the amount of RAM passed via a command line switch, the
> qemu-mips emulation sets up a Linux kernel like "command line" in
> memory where u-boot could parse it from.
>
>   
Does it, or just when you pass -kernel to it? I'll check.
>>  +}
>>  +
>>  +
>>  +int checkboard (void)
>>  +{
>>  +       u32 proc_id;
>>  +
>>  +       proc_id = read_32bit_cp0_register(CP0_PRID);
>>  +
>>  +       switch (proc_id >> 24) {
>>  +       default:
>>  +               printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
>>  +       }
>>  +
>>  +       return 0;
>>  +}
>>     
>
> Huh? What is this code good for?
>
>   
Checking for the type of board, I suppose :-)  I think all BSPs have it 
and it's called early in the boot process. I could either do only a 
return 0 or actually decode CP0_PRID and print something meaningful, if 
Qemu sets it to something sensible. Or just print a nice banner.

Thanks for the input. This is a first version and it does what it's 
supposed to do, it booted in qemu HEAD on linux-x86 and in stock 0.90 
for Windows and loaded a linux kernel via dhcp/tftp, nfs, ext2 and fat 
partitions on IDE. I say it can only go up from here :-) Any other 
suggestions are welcome, and if you don't feel like compiling it for a 
test, I can send you a binary by e-mail.


Vlad