From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1IpES1-0001OJ-WC for qemu-devel@nongnu.org; Mon, 05 Nov 2007 21:46:02 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1IpERx-0001GF-76 for qemu-devel@nongnu.org; Mon, 05 Nov 2007 21:46:01 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1IpERx-0001Fw-12 for qemu-devel@nongnu.org; Mon, 05 Nov 2007 21:45:57 -0500 Received: from pop-tawny.atl.sa.earthlink.net ([207.69.195.67]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1IpERw-0003ko-Nb for qemu-devel@nongnu.org; Mon, 05 Nov 2007 21:45:56 -0500 Received: from user-142h2k8.cable.mindspring.com ([72.40.138.136] helo=earthlink.net) by pop-tawny.atl.sa.earthlink.net with esmtp (Exim 3.36 #1) id 1IpERv-0006Sr-00 for qemu-devel@nongnu.org; Mon, 05 Nov 2007 21:45:55 -0500 Message-ID: <472FD561.7020006@earthlink.net> Date: Mon, 05 Nov 2007 21:45:53 -0500 From: Robert Reif MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------010909080905060607050501" Subject: [Qemu-devel] [PATCH] sparc32 boot mode flag fix Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. --------------010909080905060607050501 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit This patch adds CPU dependent boot mode flag support. Different CPUs use different bits for the boot mode flag. The constant MMU_BM is replaced with a variable which is set for the selected CPU. This patch also removes the MMU flags from being saved in the translation block code as a result of an off line discussion with Paul Brook. This patch also performs a CPU reset after the CPU is registered rather than before. This patch has successfully booted the debian installer and the initrd kernel in sparc-test successfully for both an ss5 and ss10. It also makes running an ss10 openboot rom image behave a little better. --------------010909080905060607050501 Content-Type: text/plain; name="mmu_bm.diff.txt" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="mmu_bm.diff.txt" Index: cpu-exec.c =================================================================== RCS file: /sources/qemu/qemu/cpu-exec.c,v retrieving revision 1.120 diff -p -u -r1.120 cpu-exec.c --- cpu-exec.c 14 Oct 2007 07:07:04 -0000 1.120 +++ cpu-exec.c 6 Nov 2007 00:12:56 -0000 @@ -181,10 +181,8 @@ static inline TranslationBlock *tb_find_ flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2)) | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2); #else - // FPU enable . MMU Boot . MMU enabled . MMU no-fault . Supervisor - flags = (env->psref << 4) | (((env->mmuregs[0] & MMU_BM) >> 14) << 3) - | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1) - | env->psrs; + // FPU enable . Supervisor + flags = (env->psref << 4) | env->psrs; #endif cs_base = env->npc; pc = env->pc; Index: target-sparc/cpu.h =================================================================== RCS file: /sources/qemu/qemu/target-sparc/cpu.h,v retrieving revision 1.56 diff -p -u -r1.56 cpu.h --- target-sparc/cpu.h 14 Oct 2007 17:07:21 -0000 1.56 +++ target-sparc/cpu.h 6 Nov 2007 00:13:00 -0000 @@ -147,7 +147,6 @@ /* MMU */ #define MMU_E (1<<0) #define MMU_NF (1<<1) -#define MMU_BM (1<<14) #define PTE_ENTRYTYPE_MASK 3 #define PTE_ACCESS_MASK 0x1c @@ -200,6 +199,7 @@ typedef struct CPUSPARCState { int interrupt_index; int interrupt_request; int halted; + uint32_t mmu_bm; /* NOTE: we allow 8 more registers to handle wrapping */ target_ulong regbase[NWINDOWS * 16 + 8]; Index: target-sparc/helper.c =================================================================== RCS file: /sources/qemu/qemu/target-sparc/helper.c,v retrieving revision 1.28 diff -p -u -r1.28 helper.c --- target-sparc/helper.c 14 Oct 2007 07:07:08 -0000 1.28 +++ target-sparc/helper.c 6 Nov 2007 00:13:00 -0000 @@ -114,7 +114,7 @@ int get_physical_address (CPUState *env, if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ // Boot mode: instruction fetches are taken from PROM - if (rw == 2 && (env->mmuregs[0] & MMU_BM)) { + if (rw == 2 && (env->mmuregs[0] & env->mmu_bm)) { *physical = 0xff0000000ULL | (address & 0x3ffffULL); *prot = PAGE_READ | PAGE_EXEC; return 0; Index: target-sparc/op_helper.c =================================================================== RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v retrieving revision 1.50 diff -p -u -r1.50 op_helper.c --- target-sparc/op_helper.c 29 Oct 2007 14:39:49 -0000 1.50 +++ target-sparc/op_helper.c 6 Nov 2007 00:13:01 -0000 @@ -493,8 +493,8 @@ void helper_st_asi(int asi, int size) oldreg = env->mmuregs[reg]; switch(reg) { case 0: - env->mmuregs[reg] &= ~(MMU_E | MMU_NF | MMU_BM); - env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | MMU_BM); + env->mmuregs[reg] &= ~(MMU_E | MMU_NF | env->mmu_bm); + env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF | env->mmu_bm); // Mappings generated during no-fault mode or MMU // disabled mode are invalid in normal mode if (oldreg != env->mmuregs[reg]) Index: target-sparc/translate.c =================================================================== RCS file: /sources/qemu/qemu/target-sparc/translate.c,v retrieving revision 1.78 diff -p -u -r1.78 translate.c --- target-sparc/translate.c 17 Oct 2007 17:34:57 -0000 1.78 +++ target-sparc/translate.c 6 Nov 2007 00:13:03 -0000 @@ -59,6 +59,7 @@ struct sparc_def_t { target_ulong iu_version; uint32_t fpu_version; uint32_t mmu_version; + uint32_t mmu_bm; }; static uint16_t *gen_opc_ptr; @@ -3482,7 +3483,7 @@ void cpu_reset(CPUSPARCState *env) #else env->pc = 0; env->mmuregs[0] &= ~(MMU_E | MMU_NF); - env->mmuregs[0] |= MMU_BM; + env->mmuregs[0] |= env->mmu_bm; #endif env->npc = env->pc + 4; #endif @@ -3496,7 +3497,6 @@ CPUSPARCState *cpu_sparc_init(void) if (!env) return NULL; cpu_exec_init(env); - cpu_reset(env); return (env); } @@ -3515,30 +3515,35 @@ static const sparc_def_t sparc_defs[] = .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ + .mmu_bm = 0x00004000, }, { .name = "Fujitsu MB86907", .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ + .mmu_bm = 0x00004000, }, { .name = "TI MicroSparc I", .iu_version = 0x41000000, .fpu_version = 4 << 17, .mmu_version = 0x41000000, + .mmu_bm = 0x00004000, }, { .name = "TI SuperSparc II", .iu_version = 0x40000000, .fpu_version = 0 << 17, .mmu_version = 0x04000000, + .mmu_bm = 0x00002000, }, { .name = "Ross RT620", .iu_version = 0x1e000000, .fpu_version = 1 << 17, .mmu_version = 0x17000000, + .mmu_bm = 0x00004000, }, #endif }; @@ -3579,9 +3584,11 @@ int cpu_sparc_register (CPUSPARCState *e env->version = def->iu_version; env->fsr = def->fpu_version; #if !defined(TARGET_SPARC64) + env->mmu_bm = def->mmu_bm; env->mmuregs[0] |= def->mmu_version; env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; #endif + cpu_reset(env); return 0; } --------------010909080905060607050501--