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From: Robert Reif <reif@earthlink.net>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [RFC][PATCH] fix sparc32 mxcc 64 bit read word order
Date: Thu, 15 Nov 2007 07:48:39 -0500	[thread overview]
Message-ID: <473C4027.3030608@earthlink.net> (raw)

[-- Attachment #1: Type: text/plain, Size: 765 bytes --]

This patch fixes the word order for 64 bit reads of the mxcc registers.

It returns the high 32 bits in ret and the lower 32 bits in T0 just
like other places in the same function.

T0 is defined as: register uint32_t T0 asm(AREG1);

T0 on my machine has a sizeof = 4.  Because of this, I don't think
it is necessary to mask off the high bits with 0xffffffff like other
places in the same function.  You should probably use 0xffffffffULL to
mask off the upper 32 bits.

I would remove the & 0xffffffff but I hesitate because T0 is defined
"register" uint32_t and I'm not sure what that would really be on 64
bit machines,

Is this patch correct or should I remove the & 0xffffffff here and in 
the other
places in the same function or change them to 0xffffffffULL?

[-- Attachment #2: mxcc.diff.txt --]
[-- Type: text/plain, Size: 1284 bytes --]

Index: target-sparc/op_helper.c
===================================================================
RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v
retrieving revision 1.52
diff -p -u -r1.52 op_helper.c
--- target-sparc/op_helper.c	11 Nov 2007 19:46:09 -0000	1.52
+++ target-sparc/op_helper.c	15 Nov 2007 12:27:05 -0000
@@ -196,8 +196,8 @@ void helper_ld_asi(int asi, int size, in
         switch (T0) {
         case 0x01c00a00: /* MXCC control register */
             if (size == 8) {
-                ret = env->mxccregs[3];
-                T0 = env->mxccregs[3] >> 32;
+                ret = env->mxccregs[3] >> 32;
+                T0 = env->mxccregs[3] & 0xffffffff;
             } else
                 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
             break;
@@ -209,8 +209,8 @@ void helper_ld_asi(int asi, int size, in
             break;
         case 0x01c00f00: /* MBus port address register */
             if (size == 8) {
-                ret = env->mxccregs[7];
-                T0 = env->mxccregs[7] >> 32;
+                ret = env->mxccregs[7] >> 32;
+                T0 = env->mxccregs[7] & 0xffffffff;
             } else
                 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
             break;

             reply	other threads:[~2007-11-15 12:48 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-11-15 12:48 Robert Reif [this message]
2007-11-15 18:10 ` [Qemu-devel] [RFC][PATCH] fix sparc32 mxcc 64 bit read word order Blue Swirl
2007-11-15 23:08   ` Robert Reif
2007-11-17  9:21     ` Blue Swirl
2007-11-18 20:57       ` Robert Reif
2007-11-18 21:10         ` Blue Swirl
2007-11-18 21:58           ` Robert Reif
2007-11-19 19:16         ` Blue Swirl

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