From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Ise9D-0002C7-En for qemu-devel@nongnu.org; Thu, 15 Nov 2007 07:48:43 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Ise9B-0002Bo-3S for qemu-devel@nongnu.org; Thu, 15 Nov 2007 07:48:42 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Ise9A-0002Bl-Ur for qemu-devel@nongnu.org; Thu, 15 Nov 2007 07:48:40 -0500 Received: from pop-scotia.atl.sa.earthlink.net ([207.69.195.65]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Ise9A-0005cC-Hx for qemu-devel@nongnu.org; Thu, 15 Nov 2007 07:48:40 -0500 Received: from user-142h2k8.cable.mindspring.com ([72.40.138.136] helo=earthlink.net) by pop-scotia.atl.sa.earthlink.net with esmtp (Exim 3.36 #1) id 1Ise99-0004Fh-00 for qemu-devel@nongnu.org; Thu, 15 Nov 2007 07:48:39 -0500 Message-ID: <473C4027.3030608@earthlink.net> Date: Thu, 15 Nov 2007 07:48:39 -0500 From: Robert Reif MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------060102070608060407020500" Subject: [Qemu-devel] [RFC][PATCH] fix sparc32 mxcc 64 bit read word order Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is a multi-part message in MIME format. --------------060102070608060407020500 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit This patch fixes the word order for 64 bit reads of the mxcc registers. It returns the high 32 bits in ret and the lower 32 bits in T0 just like other places in the same function. T0 is defined as: register uint32_t T0 asm(AREG1); T0 on my machine has a sizeof = 4. Because of this, I don't think it is necessary to mask off the high bits with 0xffffffff like other places in the same function. You should probably use 0xffffffffULL to mask off the upper 32 bits. I would remove the & 0xffffffff but I hesitate because T0 is defined "register" uint32_t and I'm not sure what that would really be on 64 bit machines, Is this patch correct or should I remove the & 0xffffffff here and in the other places in the same function or change them to 0xffffffffULL? --------------060102070608060407020500 Content-Type: text/plain; name="mxcc.diff.txt" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="mxcc.diff.txt" Index: target-sparc/op_helper.c =================================================================== RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v retrieving revision 1.52 diff -p -u -r1.52 op_helper.c --- target-sparc/op_helper.c 11 Nov 2007 19:46:09 -0000 1.52 +++ target-sparc/op_helper.c 15 Nov 2007 12:27:05 -0000 @@ -196,8 +196,8 @@ void helper_ld_asi(int asi, int size, in switch (T0) { case 0x01c00a00: /* MXCC control register */ if (size == 8) { - ret = env->mxccregs[3]; - T0 = env->mxccregs[3] >> 32; + ret = env->mxccregs[3] >> 32; + T0 = env->mxccregs[3] & 0xffffffff; } else DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); break; @@ -209,8 +209,8 @@ void helper_ld_asi(int asi, int size, in break; case 0x01c00f00: /* MBus port address register */ if (size == 8) { - ret = env->mxccregs[7]; - T0 = env->mxccregs[7] >> 32; + ret = env->mxccregs[7] >> 32; + T0 = env->mxccregs[7] & 0xffffffff; } else DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); break; --------------060102070608060407020500--