From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1IsndP-00041Q-Ap for qemu-devel@nongnu.org; Thu, 15 Nov 2007 17:56:31 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1IsndM-0003x9-K2 for qemu-devel@nongnu.org; Thu, 15 Nov 2007 17:56:30 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1IsndM-0003wh-FJ for qemu-devel@nongnu.org; Thu, 15 Nov 2007 17:56:28 -0500 Received: from pop-altamira.atl.sa.earthlink.net ([207.69.195.62]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1IsndM-0005Be-1H for qemu-devel@nongnu.org; Thu, 15 Nov 2007 17:56:28 -0500 Received: from user-142h2k8.cable.mindspring.com ([72.40.138.136] helo=earthlink.net) by pop-altamira.atl.sa.earthlink.net with esmtp (Exim 3.36 #1) id 1IsndL-0003uG-00 for qemu-devel@nongnu.org; Thu, 15 Nov 2007 17:56:27 -0500 Message-ID: <473CCE9A.1010709@earthlink.net> Date: Thu, 15 Nov 2007 17:56:26 -0500 From: Robert Reif MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH] add iommu version to sparc32 References: <4738DB62.3080008@earthlink.net> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org >>Add iommu version to sparc32. Also reset iommu after initialization. >> >> > >Should the version be tied to CPU model instead of machine type? At >least for Turbosparc this seems to be the case. > > On SMP systems the IOMMU is on the system board in a separate ASIC. On single CPU systems the IOMMU is integrated into the CPU. Without checking the FEH, the SS 5 was the only single CPU system that shipped with more than one family of CPUs (MicroSparc II and TurboSparc and they do have different IOMMU versions). That could be special cased. Unfortunately QEMU will allow you to specify unrealistic systems. We should probably add allowable CPU types to specific machine types to catch this.