From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1ItMBB-0002tP-6T for qemu-devel@nongnu.org; Sat, 17 Nov 2007 06:49:41 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1ItMB9-0002pw-BO for qemu-devel@nongnu.org; Sat, 17 Nov 2007 06:49:40 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1ItMB9-0002pp-8U for qemu-devel@nongnu.org; Sat, 17 Nov 2007 06:49:39 -0500 Received: from sp604001mt.neufgp.fr ([84.96.92.60] helo=Smtp.neuf.fr) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1ItM2w-0001nn-U7 for qemu-devel@nongnu.org; Sat, 17 Nov 2007 06:41:11 -0500 Received: from [84.102.211.23] by sp604001mt.gpm.neuf.ld (Sun Java System Messaging Server 6.2-5.05 (built Feb 16 2006)) with ESMTP id <0JRN00B0HF4ELCZ0@sp604001mt.gpm.neuf.ld> for qemu-devel@nongnu.org; Sat, 17 Nov 2007 12:41:02 +0100 (CET) Date: Sat, 17 Nov 2007 12:40:30 +0100 From: Fabrice Bellard Subject: Re: [Qemu-devel] qemu softmmu_template.h In-reply-to: Message-id: <473ED32E.80901@bellard.org> MIME-version: 1.0 Content-type: text/plain; charset=UTF-8 Content-transfer-encoding: 7BIT References: <1195293653.5335.27.camel@rapid> <1195295212.5335.36.camel@rapid> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org andrzej zaborowski wrote: > On 17/11/2007, J. Mayer wrote: >> On Sat, 2007-11-17 at 11:14 +0100, andrzej zaborowski wrote: >>> On 17/11/2007, J. Mayer wrote: >>>> On Sat, 2007-11-17 at 09:53 +0000, Andrzej Zaborowski wrote: >>>>> CVSROOT: /sources/qemu >>>>> Module name: qemu >>>>> Changes by: Andrzej Zaborowski 07/11/17 09:53:42 >>>>> >>>>> Modified files: >>>>> . : softmmu_template.h >>>>> >>>>> Log message: >>>>> Check permissions for the last byte first in unaligned slow_st accesses (patch from TeLeMan). >>>>> >>>>> CVSWeb URLs: >>>>> http://cvs.savannah.gnu.org/viewcvs/qemu/softmmu_template.h?cvsroot=qemu&r1=1.19&r2=1.20 >>>>> >>>> Has it been checked that it's legal for all architectures and cannot >>>> have any nasty side effect to do accesses in the reverse order ? Real >>>> hardware do not ever seem to do this... >>> For real hardware the store is a single operation. >> For PowerPC, at least, only aligned stores are defined as atomic. It's >> absolutely legal for an implementation to split all non-atomic accesses >> into smaller aligned accesses. And I guess it is the same for all >> architecture that can do unaligned accesses. >> >>> Logically it shouldn't have any side effects, but if it does then it >>> would rather mean that other code for that architecture is (also) >>> broken, I believe. >>> >>> I've only tested ARM, mips, x86 and x86_64 before committing, so >>> please test. I figured that the patch won't get any comments on the >>> mailing list if it isn't merged. >> I don't think it's so easy to test because it may be very hard to >> trigger the cases that would have side effects, which are target >> dependent. I then am very curious to know how you did check that there >> is no problem with this patch.... > > Well, for ARM, x86 and x86_64 I only checked that unaligned accesses > still work, i.e. that I haven't made an obvious typo. I haven't tested > cross-page accesses with the access to the second page being invalid, > I also don't know how the specifications for other architectures > define the effect of such accesses, so maybe I shouldn't have > committed this, but I assumed a common sense in the design of cpu > archs, meaning that in the example given by TeLeMan the addition is > not performed two times on some bytes. > Regards I agree with this patch is the sense that the previous behaviour was clearly incorrect. Now this patch relies on the fact that tlb_fill() does not remove the previous page from the TLB cache which is an important "hidden" constraint. Fabrice.