* [PATCH 01/11] target/ppc: receive DisasContext explicitly in GEN_PRIV
2022-06-15 19:19 [PATCH 00/11] target/ppc: Implement slbiag move slb* to decodetree Lucas Coutinho
@ 2022-06-15 19:19 ` Lucas Coutinho
2022-06-21 16:38 ` Leandro Lupori
2022-06-15 19:19 ` [PATCH 02/11] target/ppc: add macros to check privilege level Lucas Coutinho
` (10 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: Lucas Coutinho @ 2022-06-15 19:19 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, Matheus Ferst,
Lucas Coutinho
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
GEN_PRIV and related CHK_* macros just assumed that variable named
"ctx" would be in scope when they are used, and that it would be a
pointer to DisasContext. Change these macros to receive the pointer
explicitly.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
---
target/ppc/translate.c | 299 +++++++++++++++--------------
target/ppc/translate/fp-impl.c.inc | 4 +-
2 files changed, 154 insertions(+), 149 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4fcb311c2d..920bb543cf 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1267,38 +1267,43 @@ typedef struct opcode_t {
const char *oname;
} opcode_t;
+static void gen_priv_opc(DisasContext *ctx)
+{
+ gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
+}
+
/* Helpers for priv. check */
-#define GEN_PRIV \
- do { \
- gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
+#define GEN_PRIV(CTX) \
+ do { \
+ gen_priv_opc(CTX); return; \
} while (0)
#if defined(CONFIG_USER_ONLY)
-#define CHK_HV GEN_PRIV
-#define CHK_SV GEN_PRIV
-#define CHK_HVRM GEN_PRIV
+#define CHK_HV(CTX) GEN_PRIV(CTX)
+#define CHK_SV(CTX) GEN_PRIV(CTX)
+#define CHK_HVRM(CTX) GEN_PRIV(CTX)
#else
-#define CHK_HV \
- do { \
- if (unlikely(ctx->pr || !ctx->hv)) { \
- GEN_PRIV; \
- } \
+#define CHK_HV(CTX) \
+ do { \
+ if (unlikely(ctx->pr || !ctx->hv)) {\
+ GEN_PRIV(CTX); \
+ } \
} while (0)
-#define CHK_SV \
+#define CHK_SV(CTX) \
do { \
if (unlikely(ctx->pr)) { \
- GEN_PRIV; \
+ GEN_PRIV(CTX); \
} \
} while (0)
-#define CHK_HVRM \
- do { \
- if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
- GEN_PRIV; \
- } \
+#define CHK_HVRM(CTX) \
+ do { \
+ if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
+ GEN_PRIV(CTX); \
+ } \
} while (0)
#endif
-#define CHK_NONE
+#define CHK_NONE(CTX)
/*****************************************************************************/
/* PowerPC instructions table */
@@ -3252,7 +3257,7 @@ GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ))
static void glue(gen_, name##x)(DisasContext *ctx) \
{ \
TCGv EA; \
- chk; \
+ chk(ctx); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
@@ -3270,7 +3275,7 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
static void glue(gen_, name##epx)(DisasContext *ctx) \
{ \
TCGv EA; \
- CHK_SV; \
+ CHK_SV(ctx); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
@@ -3298,7 +3303,7 @@ GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
static void glue(gen_, name##x)(DisasContext *ctx) \
{ \
TCGv EA; \
- chk; \
+ chk(ctx); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
@@ -3315,7 +3320,7 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
static void glue(gen_, name##epx)(DisasContext *ctx) \
{ \
TCGv EA; \
- CHK_SV; \
+ CHK_SV(ctx); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
@@ -4078,11 +4083,11 @@ static void gen_wait(DisasContext *ctx)
static void gen_doze(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv_i32 t;
- CHK_HV;
+ CHK_HV(ctx);
t = tcg_const_i32(PPC_PM_DOZE);
gen_helper_pminsn(cpu_env, t);
tcg_temp_free_i32(t);
@@ -4094,11 +4099,11 @@ static void gen_doze(DisasContext *ctx)
static void gen_nap(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv_i32 t;
- CHK_HV;
+ CHK_HV(ctx);
t = tcg_const_i32(PPC_PM_NAP);
gen_helper_pminsn(cpu_env, t);
tcg_temp_free_i32(t);
@@ -4110,11 +4115,11 @@ static void gen_nap(DisasContext *ctx)
static void gen_stop(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv_i32 t;
- CHK_HV;
+ CHK_HV(ctx);
t = tcg_const_i32(PPC_PM_STOP);
gen_helper_pminsn(cpu_env, t);
tcg_temp_free_i32(t);
@@ -4126,11 +4131,11 @@ static void gen_stop(DisasContext *ctx)
static void gen_sleep(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv_i32 t;
- CHK_HV;
+ CHK_HV(ctx);
t = tcg_const_i32(PPC_PM_SLEEP);
gen_helper_pminsn(cpu_env, t);
tcg_temp_free_i32(t);
@@ -4142,11 +4147,11 @@ static void gen_sleep(DisasContext *ctx)
static void gen_rvwinkle(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv_i32 t;
- CHK_HV;
+ CHK_HV(ctx);
t = tcg_const_i32(PPC_PM_RVWINKLE);
gen_helper_pminsn(cpu_env, t);
tcg_temp_free_i32(t);
@@ -4476,7 +4481,7 @@ static void gen_mcrf(DisasContext *ctx)
static void gen_rfi(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
/*
* This instruction doesn't exist anymore on 64-bit server
@@ -4487,7 +4492,7 @@ static void gen_rfi(DisasContext *ctx)
return;
}
/* Restore CPU state */
- CHK_SV;
+ CHK_SV(ctx);
gen_icount_io_start(ctx);
gen_update_cfar(ctx, ctx->cia);
gen_helper_rfi(cpu_env);
@@ -4499,10 +4504,10 @@ static void gen_rfi(DisasContext *ctx)
static void gen_rfid(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
/* Restore CPU state */
- CHK_SV;
+ CHK_SV(ctx);
gen_icount_io_start(ctx);
gen_update_cfar(ctx, ctx->cia);
gen_helper_rfid(cpu_env);
@@ -4514,10 +4519,10 @@ static void gen_rfid(DisasContext *ctx)
static void gen_rfscv(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
/* Restore CPU state */
- CHK_SV;
+ CHK_SV(ctx);
gen_icount_io_start(ctx);
gen_update_cfar(ctx, ctx->cia);
gen_helper_rfscv(cpu_env);
@@ -4529,10 +4534,10 @@ static void gen_rfscv(DisasContext *ctx)
static void gen_hrfid(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
/* Restore CPU state */
- CHK_HV;
+ CHK_HV(ctx);
gen_helper_hrfid(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
#endif
@@ -4733,7 +4738,7 @@ static void gen_mfcr(DisasContext *ctx)
/* mfmsr */
static void gen_mfmsr(DisasContext *ctx)
{
- CHK_SV;
+ CHK_SV(ctx);
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
}
@@ -4847,7 +4852,7 @@ static void gen_mtmsrd(DisasContext *ctx)
return;
}
- CHK_SV;
+ CHK_SV(ctx);
#if !defined(CONFIG_USER_ONLY)
TCGv t0, t1;
@@ -4890,7 +4895,7 @@ static void gen_mtmsrd(DisasContext *ctx)
static void gen_mtmsr(DisasContext *ctx)
{
- CHK_SV;
+ CHK_SV(ctx);
#if !defined(CONFIG_USER_ONLY)
TCGv t0, t1;
@@ -5022,7 +5027,7 @@ static void gen_dcbfep(DisasContext *ctx)
{
/* XXX: specification says this is treated as a load by the MMU */
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
gen_set_access_type(ctx, ACCESS_CACHE);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
@@ -5034,11 +5039,11 @@ static void gen_dcbfep(DisasContext *ctx)
static void gen_dcbi(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv EA, val;
- CHK_SV;
+ CHK_SV(ctx);
EA = tcg_temp_new();
gen_set_access_type(ctx, ACCESS_CACHE);
gen_addr_reg_index(ctx, EA);
@@ -5223,11 +5228,11 @@ static void gen_dcba(DisasContext *ctx)
static void gen_mfsr(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_const_tl(SR(ctx->opcode));
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
tcg_temp_free(t0);
@@ -5238,11 +5243,11 @@ static void gen_mfsr(DisasContext *ctx)
static void gen_mfsrin(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_temp_new();
tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
@@ -5254,11 +5259,11 @@ static void gen_mfsrin(DisasContext *ctx)
static void gen_mtsr(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_const_tl(SR(ctx->opcode));
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
tcg_temp_free(t0);
@@ -5269,10 +5274,10 @@ static void gen_mtsr(DisasContext *ctx)
static void gen_mtsrin(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_temp_new();
tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
@@ -5288,11 +5293,11 @@ static void gen_mtsrin(DisasContext *ctx)
static void gen_mfsr_64b(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_const_tl(SR(ctx->opcode));
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
tcg_temp_free(t0);
@@ -5303,11 +5308,11 @@ static void gen_mfsr_64b(DisasContext *ctx)
static void gen_mfsrin_64b(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_temp_new();
tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
@@ -5319,11 +5324,11 @@ static void gen_mfsrin_64b(DisasContext *ctx)
static void gen_mtsr_64b(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_const_tl(SR(ctx->opcode));
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
tcg_temp_free(t0);
@@ -5334,11 +5339,11 @@ static void gen_mtsr_64b(DisasContext *ctx)
static void gen_mtsrin_64b(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_temp_new();
tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
@@ -5350,9 +5355,9 @@ static void gen_mtsrin_64b(DisasContext *ctx)
static void gen_slbmte(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
cpu_gpr[rS(ctx->opcode)]);
@@ -5362,9 +5367,9 @@ static void gen_slbmte(DisasContext *ctx)
static void gen_slbmfee(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
cpu_gpr[rB(ctx->opcode)]);
@@ -5374,9 +5379,9 @@ static void gen_slbmfee(DisasContext *ctx)
static void gen_slbmfev(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
cpu_gpr[rB(ctx->opcode)]);
@@ -5416,9 +5421,9 @@ static void gen_slbfee_(DisasContext *ctx)
static void gen_tlbia(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_HV;
+ CHK_HV(ctx);
gen_helper_tlbia(cpu_env);
#endif /* defined(CONFIG_USER_ONLY) */
@@ -5428,13 +5433,13 @@ static void gen_tlbia(DisasContext *ctx)
static void gen_tlbsync(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
if (ctx->gtse) {
- CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */
+ CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */
} else {
- CHK_HV; /* Else hypervisor privileged */
+ CHK_HV(ctx); /* Else hypervisor privileged */
}
/* BookS does both ptesync and tlbsync make tlbsync a nop for server */
@@ -5449,12 +5454,12 @@ static void gen_tlbsync(DisasContext *ctx)
static void gen_slbia(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
uint32_t ih = (ctx->opcode >> 21) & 0x7;
TCGv_i32 t0 = tcg_const_i32(ih);
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_slbia(cpu_env, t0);
tcg_temp_free_i32(t0);
@@ -5465,9 +5470,9 @@ static void gen_slbia(DisasContext *ctx)
static void gen_slbie(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
@@ -5477,9 +5482,9 @@ static void gen_slbie(DisasContext *ctx)
static void gen_slbieg(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
@@ -5489,9 +5494,9 @@ static void gen_slbieg(DisasContext *ctx)
static void gen_slbsync(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_check_tlb_flush(ctx, true);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -5533,9 +5538,9 @@ static void gen_ecowx(DisasContext *ctx)
static void gen_tlbld_6xx(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -5544,9 +5549,9 @@ static void gen_tlbld_6xx(DisasContext *ctx)
static void gen_tlbli_6xx(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -5564,11 +5569,11 @@ static void gen_mfapidi(DisasContext *ctx)
static void gen_tlbiva(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
@@ -5795,11 +5800,11 @@ GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
static void gen_mfdcr(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv dcrn;
- CHK_SV;
+ CHK_SV(ctx);
dcrn = tcg_const_tl(SPR(ctx->opcode));
gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
tcg_temp_free(dcrn);
@@ -5810,11 +5815,11 @@ static void gen_mfdcr(DisasContext *ctx)
static void gen_mtdcr(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv dcrn;
- CHK_SV;
+ CHK_SV(ctx);
dcrn = tcg_const_tl(SPR(ctx->opcode));
gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
tcg_temp_free(dcrn);
@@ -5826,9 +5831,9 @@ static void gen_mtdcr(DisasContext *ctx)
static void gen_mfdcrx(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
cpu_gpr[rA(ctx->opcode)]);
/* Note: Rc update flag set leads to undefined state of Rc0 */
@@ -5840,9 +5845,9 @@ static void gen_mfdcrx(DisasContext *ctx)
static void gen_mtdcrx(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
cpu_gpr[rS(ctx->opcode)]);
/* Note: Rc update flag set leads to undefined state of Rc0 */
@@ -5868,7 +5873,7 @@ static void gen_mtdcrux(DisasContext *ctx)
/* dccci */
static void gen_dccci(DisasContext *ctx)
{
- CHK_SV;
+ CHK_SV(ctx);
/* interpreted as no-op */
}
@@ -5876,11 +5881,11 @@ static void gen_dccci(DisasContext *ctx)
static void gen_dcread(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv EA, val;
- CHK_SV;
+ CHK_SV(ctx);
gen_set_access_type(ctx, ACCESS_CACHE);
EA = tcg_temp_new();
gen_addr_reg_index(ctx, EA);
@@ -5905,14 +5910,14 @@ static void gen_icbt_40x(DisasContext *ctx)
/* iccci */
static void gen_iccci(DisasContext *ctx)
{
- CHK_SV;
+ CHK_SV(ctx);
/* interpreted as no-op */
}
/* icread */
static void gen_icread(DisasContext *ctx)
{
- CHK_SV;
+ CHK_SV(ctx);
/* interpreted as no-op */
}
@@ -5920,9 +5925,9 @@ static void gen_icread(DisasContext *ctx)
static void gen_rfci_40x(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
/* Restore CPU state */
gen_helper_40x_rfci(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
@@ -5932,9 +5937,9 @@ static void gen_rfci_40x(DisasContext *ctx)
static void gen_rfci(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
/* Restore CPU state */
gen_helper_rfci(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
@@ -5947,9 +5952,9 @@ static void gen_rfci(DisasContext *ctx)
static void gen_rfdi(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
/* Restore CPU state */
gen_helper_rfdi(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
@@ -5960,9 +5965,9 @@ static void gen_rfdi(DisasContext *ctx)
static void gen_rfmci(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
/* Restore CPU state */
gen_helper_rfmci(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
@@ -5975,9 +5980,9 @@ static void gen_rfmci(DisasContext *ctx)
static void gen_tlbre_40x(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
switch (rB(ctx->opcode)) {
case 0:
gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
@@ -5998,11 +6003,11 @@ static void gen_tlbre_40x(DisasContext *ctx)
static void gen_tlbsx_40x(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
@@ -6021,9 +6026,9 @@ static void gen_tlbsx_40x(DisasContext *ctx)
static void gen_tlbwe_40x(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
switch (rB(ctx->opcode)) {
case 0:
@@ -6047,9 +6052,9 @@ static void gen_tlbwe_40x(DisasContext *ctx)
static void gen_tlbre_440(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
switch (rB(ctx->opcode)) {
case 0:
@@ -6073,11 +6078,11 @@ static void gen_tlbre_440(DisasContext *ctx)
static void gen_tlbsx_440(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
@@ -6096,9 +6101,9 @@ static void gen_tlbsx_440(DisasContext *ctx)
static void gen_tlbwe_440(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
switch (rB(ctx->opcode)) {
case 0:
case 1:
@@ -6123,9 +6128,9 @@ static void gen_tlbwe_440(DisasContext *ctx)
static void gen_tlbre_booke206(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_booke206_tlbre(cpu_env);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -6134,11 +6139,11 @@ static void gen_tlbre_booke206(DisasContext *ctx)
static void gen_tlbsx_booke206(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
if (rA(ctx->opcode)) {
t0 = tcg_temp_new();
tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
@@ -6156,9 +6161,9 @@ static void gen_tlbsx_booke206(DisasContext *ctx)
static void gen_tlbwe_booke206(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_booke206_tlbwe(cpu_env);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -6166,11 +6171,11 @@ static void gen_tlbwe_booke206(DisasContext *ctx)
static void gen_tlbivax_booke206(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
gen_helper_booke206_tlbivax(cpu_env, t0);
@@ -6181,11 +6186,11 @@ static void gen_tlbivax_booke206(DisasContext *ctx)
static void gen_tlbilx_booke206(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
@@ -6213,11 +6218,11 @@ static void gen_tlbilx_booke206(DisasContext *ctx)
static void gen_wrtee(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
@@ -6235,9 +6240,9 @@ static void gen_wrtee(DisasContext *ctx)
static void gen_wrteei(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
if (ctx->opcode & 0x00008000) {
tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
/* Stop translation to have a chance to raise an exception */
@@ -6291,9 +6296,9 @@ static void gen_icbt_440(DisasContext *ctx)
static void gen_msgclr(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_HV;
+ CHK_HV(ctx);
if (is_book3s_arch2x(ctx)) {
gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
} else {
@@ -6305,9 +6310,9 @@ static void gen_msgclr(DisasContext *ctx)
static void gen_msgsnd(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_HV;
+ CHK_HV(ctx);
if (is_book3s_arch2x(ctx)) {
gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]);
} else {
@@ -6320,9 +6325,9 @@ static void gen_msgsnd(DisasContext *ctx)
static void gen_msgclrp(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -6330,9 +6335,9 @@ static void gen_msgclrp(DisasContext *ctx)
static void gen_msgsndp(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -6341,9 +6346,9 @@ static void gen_msgsndp(DisasContext *ctx)
static void gen_msgsync(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_HV;
+ CHK_HV(ctx);
#endif /* defined(CONFIG_USER_ONLY) */
/* interpreted as no-op */
}
@@ -6454,7 +6459,7 @@ static void gen_tcheck(DisasContext *ctx)
#define GEN_TM_PRIV_NOOP(name) \
static inline void gen_##name(DisasContext *ctx) \
{ \
- gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
+ gen_priv_opc(ctx); \
}
#else
@@ -6462,7 +6467,7 @@ static inline void gen_##name(DisasContext *ctx) \
#define GEN_TM_PRIV_NOOP(name) \
static inline void gen_##name(DisasContext *ctx) \
{ \
- CHK_SV; \
+ CHK_SV(ctx); \
if (unlikely(!ctx->tm_enabled)) { \
gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
return; \
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index f9b58b844e..85b2630328 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -880,7 +880,7 @@ static void gen_lfdepx(DisasContext *ctx)
{
TCGv EA;
TCGv_i64 t0;
- CHK_SV;
+ CHK_SV(ctx);
if (unlikely(!ctx->fpu_enabled)) {
gen_exception(ctx, POWERPC_EXCP_FPU);
return;
@@ -1037,7 +1037,7 @@ static void gen_stfdepx(DisasContext *ctx)
{
TCGv EA;
TCGv_i64 t0;
- CHK_SV;
+ CHK_SV(ctx);
if (unlikely(!ctx->fpu_enabled)) {
gen_exception(ctx, POWERPC_EXCP_FPU);
return;
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH 01/11] target/ppc: receive DisasContext explicitly in GEN_PRIV
2022-06-15 19:19 ` [PATCH 01/11] target/ppc: receive DisasContext explicitly in GEN_PRIV Lucas Coutinho
@ 2022-06-21 16:38 ` Leandro Lupori
0 siblings, 0 replies; 24+ messages in thread
From: Leandro Lupori @ 2022-06-21 16:38 UTC (permalink / raw)
To: Lucas Coutinho, qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, Matheus Ferst
On 6/15/22 16:19, Lucas Coutinho wrote:
>
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
>
> GEN_PRIV and related CHK_* macros just assumed that variable named
> "ctx" would be in scope when they are used, and that it would be a
> pointer to DisasContext. Change these macros to receive the pointer
> explicitly.
>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
> Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
> ---
Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Thanks,
Leandro
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 02/11] target/ppc: add macros to check privilege level
2022-06-15 19:19 [PATCH 00/11] target/ppc: Implement slbiag move slb* to decodetree Lucas Coutinho
2022-06-15 19:19 ` [PATCH 01/11] target/ppc: receive DisasContext explicitly in GEN_PRIV Lucas Coutinho
@ 2022-06-15 19:19 ` Lucas Coutinho
2022-06-21 16:39 ` Leandro Lupori
2022-06-15 19:19 ` [PATCH 03/11] target/ppc: Move slbie to decodetree Lucas Coutinho
` (9 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: Lucas Coutinho @ 2022-06-15 19:19 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, Matheus Ferst,
Lucas Coutinho
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Equivalent to CHK_SV and CHK_HV, but can be used in decodetree methods.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
---
target/ppc/translate.c | 21 +++++++++++++++++++++
target/ppc/translate/fixedpoint-impl.c.inc | 7 ++-----
2 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 920bb543cf..508ef6660d 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6575,6 +6575,27 @@ static int times_16(DisasContext *ctx, int x)
} \
} while (0)
+#if !defined(CONFIG_USER_ONLY)
+#define REQUIRE_SV(CTX) \
+ do { \
+ if (unlikely((CTX)->pr)) { \
+ gen_priv_opc(CTX); \
+ return true; \
+ } \
+ } while (0)
+
+#define REQUIRE_HV(CTX) \
+ do { \
+ if (unlikely((CTX)->pr || !(CTX)->hv)) \
+ gen_priv_opc(CTX); \
+ return true; \
+ } \
+ } while (0)
+#else
+#define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0)
+#define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0)
+#endif
+
/*
* Helpers for implementing sets of trans_* functions.
* Defer the implementation of NAME to FUNC, with optional extra arguments.
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 1aab32be03..77d449c3cd 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -79,11 +79,8 @@ static bool do_ldst_quad(DisasContext *ctx, arg_D *a, bool store, bool prefixed)
REQUIRE_INSNS_FLAGS(ctx, 64BX);
if (!prefixed && !(ctx->insns_flags2 & PPC2_LSQ_ISA207)) {
- if (ctx->pr) {
- /* lq and stq were privileged prior to V. 2.07 */
- gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
- return true;
- }
+ /* lq and stq were privileged prior to V. 2.07 */
+ REQUIRE_SV(ctx);
if (ctx->le_mode) {
gen_align_no_le(ctx);
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH 02/11] target/ppc: add macros to check privilege level
2022-06-15 19:19 ` [PATCH 02/11] target/ppc: add macros to check privilege level Lucas Coutinho
@ 2022-06-21 16:39 ` Leandro Lupori
0 siblings, 0 replies; 24+ messages in thread
From: Leandro Lupori @ 2022-06-21 16:39 UTC (permalink / raw)
To: Lucas Coutinho, qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, Matheus Ferst
On 6/15/22 16:19, Lucas Coutinho wrote:
>
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
>
> Equivalent to CHK_SV and CHK_HV, but can be used in decodetree methods.
>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
> Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
> ---
Reviewed-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Thanks,
Leandro
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 03/11] target/ppc: Move slbie to decodetree
2022-06-15 19:19 [PATCH 00/11] target/ppc: Implement slbiag move slb* to decodetree Lucas Coutinho
2022-06-15 19:19 ` [PATCH 01/11] target/ppc: receive DisasContext explicitly in GEN_PRIV Lucas Coutinho
2022-06-15 19:19 ` [PATCH 02/11] target/ppc: add macros to check privilege level Lucas Coutinho
@ 2022-06-15 19:19 ` Lucas Coutinho
2022-06-21 16:40 ` Leandro Lupori
2022-06-15 19:19 ` [PATCH 04/11] target/ppc: Move slbieg " Lucas Coutinho
` (8 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: Lucas Coutinho @ 2022-06-15 19:19 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, Lucas Coutinho
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 7 +++++++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 13 -------------
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++++++++++++++
5 files changed, 23 insertions(+), 15 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 0b2bc8020b..793f307ab0 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -687,7 +687,7 @@ DEF_HELPER_2(load_slb_esid, tl, env, tl)
DEF_HELPER_2(load_slb_vsid, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
DEF_HELPER_FLAGS_2(slbia, TCG_CALL_NO_RWG, void, env, i32)
-DEF_HELPER_FLAGS_2(slbie, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(slbieg, TCG_CALL_NO_RWG, void, env, tl)
#endif
DEF_HELPER_FLAGS_2(load_sr, TCG_CALL_NO_RWG, tl, env, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 44ac5f0785..af13625832 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -131,6 +131,9 @@
&X_imm8 xt imm:uint8_t
@X_imm8 ...... ..... .. imm:8 .......... . &X_imm8 xt=%x_xt
+&X_rb rb
+@X_rb ...... ..... ..... rb:5 .......... . &X_rb
+
&X_uim5 xt uim:uint8_t
@X_uim5 ...... ..... ..... uim:5 .......... . &X_uim5 xt=%x_xt
@@ -787,6 +790,10 @@ XVF64GERPN 111011 ... -- .... 0 ..... 10111010 ..- @XX3_at xa=%xx_xa_pair
XVF64GERNP 111011 ... -- .... 0 ..... 01111010 ..- @XX3_at xa=%xx_xa_pair
XVF64GERNN 111011 ... -- .... 0 ..... 11111010 ..- @XX3_at xa=%xx_xa_pair
+## SLB Management Instructions
+
+SLBIE 011111 ----- ----- ..... 0110110010 - @X_rb
+
## TLB Management Instructions
&X_tlbie rb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index da9fe99ff8..03f71a82ec 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -197,7 +197,7 @@ static void __helper_slbie(CPUPPCState *env, target_ulong addr,
}
}
-void helper_slbie(CPUPPCState *env, target_ulong addr)
+void helper_SLBIE(CPUPPCState *env, target_ulong addr)
{
__helper_slbie(env, addr, false);
}
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 508ef6660d..b0bb67b676 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5466,18 +5466,6 @@ static void gen_slbia(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-/* slbie */
-static void gen_slbie(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV(ctx);
-#else
- CHK_SV(ctx);
-
- gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
/* slbieg */
static void gen_slbieg(DisasContext *ctx)
{
@@ -6910,7 +6898,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
#if defined(TARGET_PPC64)
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
-GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
#endif
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc
index f9e4a807f2..41fc5ade8b 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -21,6 +21,20 @@
* Store Control Instructions
*/
+static bool trans_SLBIE(DisasContext *ctx, arg_SLBIE *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS(ctx, SLBI);
+ REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+ gen_helper_SLBIE(cpu_env, cpu_gpr[a->rb]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 04/11] target/ppc: Move slbieg to decodetree
2022-06-15 19:19 [PATCH 00/11] target/ppc: Implement slbiag move slb* to decodetree Lucas Coutinho
` (2 preceding siblings ...)
2022-06-15 19:19 ` [PATCH 03/11] target/ppc: Move slbie to decodetree Lucas Coutinho
@ 2022-06-15 19:19 ` Lucas Coutinho
2022-06-21 16:40 ` Leandro Lupori
2022-06-15 19:20 ` [PATCH 05/11] target/ppc: Move slbia " Lucas Coutinho
` (7 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: Lucas Coutinho @ 2022-06-15 19:19 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, Lucas Coutinho
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 1 +
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 13 -------------
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++++++++++++++
5 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 793f307ab0..86cd12f399 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -688,7 +688,7 @@ DEF_HELPER_2(load_slb_vsid, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
DEF_HELPER_FLAGS_2(slbia, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
-DEF_HELPER_FLAGS_2(slbieg, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
#endif
DEF_HELPER_FLAGS_2(load_sr, TCG_CALL_NO_RWG, tl, env, tl)
DEF_HELPER_FLAGS_3(store_sr, TCG_CALL_NO_RWG, void, env, tl, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index af13625832..b900fd8f17 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -793,6 +793,7 @@ XVF64GERNN 111011 ... -- .... 0 ..... 11111010 ..- @XX3_at xa=%xx_xa_pair
## SLB Management Instructions
SLBIE 011111 ----- ----- ..... 0110110010 - @X_rb
+SLBIEG 011111 ..... ----- ..... 0111010010 - @X_tb
## TLB Management Instructions
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 03f71a82ec..a842fbd6f6 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -202,7 +202,7 @@ void helper_SLBIE(CPUPPCState *env, target_ulong addr)
__helper_slbie(env, addr, false);
}
-void helper_slbieg(CPUPPCState *env, target_ulong addr)
+void helper_SLBIEG(CPUPPCState *env, target_ulong addr)
{
__helper_slbie(env, addr, true);
}
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b0bb67b676..6e47b81bf7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5466,18 +5466,6 @@ static void gen_slbia(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-/* slbieg */
-static void gen_slbieg(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV(ctx);
-#else
- CHK_SV(ctx);
-
- gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
/* slbsync */
static void gen_slbsync(DisasContext *ctx)
{
@@ -6898,7 +6886,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
#if defined(TARGET_PPC64)
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
-GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
#endif
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc
index 41fc5ade8b..b9bb950f7d 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -35,6 +35,20 @@ static bool trans_SLBIE(DisasContext *ctx, arg_SLBIE *a)
return true;
}
+static bool trans_SLBIEG(DisasContext *ctx, arg_SLBIEG *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+ gen_helper_SLBIEG(cpu_env, cpu_gpr[a->rb]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 05/11] target/ppc: Move slbia to decodetree
2022-06-15 19:19 [PATCH 00/11] target/ppc: Implement slbiag move slb* to decodetree Lucas Coutinho
` (3 preceding siblings ...)
2022-06-15 19:19 ` [PATCH 04/11] target/ppc: Move slbieg " Lucas Coutinho
@ 2022-06-15 19:20 ` Lucas Coutinho
2022-06-21 16:52 ` Leandro Lupori
2022-06-15 19:20 ` [PATCH 06/11] target/ppc: Move slbmte " Lucas Coutinho
` (6 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: Lucas Coutinho @ 2022-06-15 19:20 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, Lucas Coutinho
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 5 +++++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 17 -----------------
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++++++++++++++
5 files changed, 21 insertions(+), 19 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 86cd12f399..4fbabda2f6 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -686,7 +686,7 @@ DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, env, tl, tl)
DEF_HELPER_2(load_slb_esid, tl, env, tl)
DEF_HELPER_2(load_slb_vsid, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
-DEF_HELPER_FLAGS_2(slbia, TCG_CALL_NO_RWG, void, env, i32)
+DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
#endif
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index b900fd8f17..c378b34b58 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -131,6 +131,9 @@
&X_imm8 xt imm:uint8_t
@X_imm8 ...... ..... .. imm:8 .......... . &X_imm8 xt=%x_xt
+&X_ih ih:uint8_t
+@X_ih ...... .. ih:3 ..... ..... .......... . &X_ih
+
&X_rb rb
@X_rb ...... ..... ..... rb:5 .......... . &X_rb
@@ -795,6 +798,8 @@ XVF64GERNN 111011 ... -- .... 0 ..... 11111010 ..- @XX3_at xa=%xx_xa_pair
SLBIE 011111 ----- ----- ..... 0110110010 - @X_rb
SLBIEG 011111 ..... ----- ..... 0111010010 - @X_tb
+SLBIA 011111 --... ----- ----- 0111110010 - @X_ih
+
## TLB Management Instructions
&X_tlbie rb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index a842fbd6f6..dd2c7e588f 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -101,7 +101,7 @@ void dump_slb(PowerPCCPU *cpu)
}
#ifdef CONFIG_TCG
-void helper_slbia(CPUPPCState *env, uint32_t ih)
+void helper_SLBIA(CPUPPCState *env, uint32_t ih)
{
PowerPCCPU *cpu = env_archcpu(env);
int starting_entry;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 6e47b81bf7..cf83890f82 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5450,22 +5450,6 @@ static void gen_tlbsync(DisasContext *ctx)
}
#if defined(TARGET_PPC64)
-/* slbia */
-static void gen_slbia(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV(ctx);
-#else
- uint32_t ih = (ctx->opcode >> 21) & 0x7;
- TCGv_i32 t0 = tcg_const_i32(ih);
-
- CHK_SV(ctx);
-
- gen_helper_slbia(cpu_env, t0);
- tcg_temp_free_i32(t0);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
/* slbsync */
static void gen_slbsync(DisasContext *ctx)
{
@@ -6885,7 +6869,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
*/
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
#if defined(TARGET_PPC64)
-GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
#endif
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc
index b9bb950f7d..cbb8b81f13 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -49,6 +49,20 @@ static bool trans_SLBIEG(DisasContext *ctx, arg_SLBIEG *a)
return true;
}
+static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS(ctx, SLBI);
+ REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+ gen_helper_SLBIA(cpu_env, tcg_constant_i32(a->ih));
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 06/11] target/ppc: Move slbmte to decodetree
2022-06-15 19:19 [PATCH 00/11] target/ppc: Implement slbiag move slb* to decodetree Lucas Coutinho
` (4 preceding siblings ...)
2022-06-15 19:20 ` [PATCH 05/11] target/ppc: Move slbia " Lucas Coutinho
@ 2022-06-15 19:20 ` Lucas Coutinho
2022-06-21 16:53 ` Leandro Lupori
2022-06-15 19:20 ` [PATCH 07/11] target/ppc: Move slbmfev " Lucas Coutinho
` (5 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: Lucas Coutinho @ 2022-06-15 19:20 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, Lucas Coutinho
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 2 ++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 14 --------------
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++++++++++++++
5 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 4fbabda2f6..acfb360e59 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -682,7 +682,7 @@ DEF_HELPER_FLAGS_2(tlbiva, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_4(tlbie_isa300, TCG_CALL_NO_WG, void, \
env, tl, tl, i32)
-DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, env, tl, tl)
+DEF_HELPER_FLAGS_3(SLBMTE, TCG_CALL_NO_RWG, void, env, tl, tl)
DEF_HELPER_2(load_slb_esid, tl, env, tl)
DEF_HELPER_2(load_slb_vsid, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index c378b34b58..00d033559f 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -800,6 +800,8 @@ SLBIEG 011111 ..... ----- ..... 0111010010 - @X_tb
SLBIA 011111 --... ----- ----- 0111110010 - @X_ih
+SLBMTE 011111 ..... ----- ..... 0110010010 - @X_tb
+
## TLB Management Instructions
&X_tlbie rb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index dd2c7e588f..1922960608 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -309,7 +309,7 @@ static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
return 0;
}
-void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
+void helper_SLBMTE(CPUPPCState *env, target_ulong rb, target_ulong rs)
{
PowerPCCPU *cpu = env_archcpu(env);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index cf83890f82..efd00c7f77 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5351,19 +5351,6 @@ static void gen_mtsrin_64b(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-/* slbmte */
-static void gen_slbmte(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV(ctx);
-#else
- CHK_SV(ctx);
-
- gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
- cpu_gpr[rS(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
static void gen_slbmfee(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
@@ -6857,7 +6844,6 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
PPC_SEGMENT_64B),
-GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc
index cbb8b81f13..4c2dd758b5 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -63,6 +63,20 @@ static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a)
return true;
}
+static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+ REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+ gen_helper_SLBMTE(cpu_env, cpu_gpr[a->rb], cpu_gpr[a->rt]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 07/11] target/ppc: Move slbmfev to decodetree
2022-06-15 19:19 [PATCH 00/11] target/ppc: Implement slbiag move slb* to decodetree Lucas Coutinho
` (5 preceding siblings ...)
2022-06-15 19:20 ` [PATCH 06/11] target/ppc: Move slbmte " Lucas Coutinho
@ 2022-06-15 19:20 ` Lucas Coutinho
2022-06-21 16:53 ` Leandro Lupori
2022-06-15 19:20 ` [PATCH 08/11] target/ppc: Move slbmfee " Lucas Coutinho
` (4 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: Lucas Coutinho @ 2022-06-15 19:20 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, Lucas Coutinho
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 2 ++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 12 ------------
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++++++++++++++
5 files changed, 18 insertions(+), 14 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index acfb360e59..dee6dfe6f4 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -684,7 +684,7 @@ DEF_HELPER_FLAGS_4(tlbie_isa300, TCG_CALL_NO_WG, void, \
env, tl, tl, i32)
DEF_HELPER_FLAGS_3(SLBMTE, TCG_CALL_NO_RWG, void, env, tl, tl)
DEF_HELPER_2(load_slb_esid, tl, env, tl)
-DEF_HELPER_2(load_slb_vsid, tl, env, tl)
+DEF_HELPER_2(SLBMFEV, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 00d033559f..c0239335a1 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -802,6 +802,8 @@ SLBIA 011111 --... ----- ----- 0111110010 - @X_ih
SLBMTE 011111 ..... ----- ..... 0110010010 - @X_tb
+SLBMFEV 011111 ..... ----- ..... 1101010011 - @X_tb
+
## TLB Management Instructions
&X_tlbie rb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 1922960608..7854b91043 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -343,7 +343,7 @@ target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb)
return rt;
}
-target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
+target_ulong helper_SLBMFEV(CPUPPCState *env, target_ulong rb)
{
PowerPCCPU *cpu = env_archcpu(env);
target_ulong rt = 0;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index efd00c7f77..f0fc375b0c 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5363,17 +5363,6 @@ static void gen_slbmfee(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-static void gen_slbmfev(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV(ctx);
-#else
- CHK_SV(ctx);
-
- gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
- cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
static void gen_slbfee_(DisasContext *ctx)
{
@@ -6845,7 +6834,6 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
PPC_SEGMENT_64B),
GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
-GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
#endif
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc
index 4c2dd758b5..a037fc2b95 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -77,6 +77,20 @@ static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a)
return true;
}
+static bool trans_SLBMFEV(DisasContext *ctx, arg_SLBMFEV *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+ REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+ gen_helper_SLBMFEV(cpu_gpr[a->rt], cpu_env, cpu_gpr[a->rb]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 08/11] target/ppc: Move slbmfee to decodetree
2022-06-15 19:19 [PATCH 00/11] target/ppc: Implement slbiag move slb* to decodetree Lucas Coutinho
` (6 preceding siblings ...)
2022-06-15 19:20 ` [PATCH 07/11] target/ppc: Move slbmfev " Lucas Coutinho
@ 2022-06-15 19:20 ` Lucas Coutinho
2022-06-21 16:54 ` Leandro Lupori
2022-06-15 19:20 ` [PATCH 09/11] target/ppc: Move slbfee " Lucas Coutinho
` (3 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: Lucas Coutinho @ 2022-06-15 19:20 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, Lucas Coutinho
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 1 +
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 13 -------------
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++++++++++++++
5 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index dee6dfe6f4..271dd585e0 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -683,7 +683,7 @@ DEF_HELPER_FLAGS_2(tlbiva, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_4(tlbie_isa300, TCG_CALL_NO_WG, void, \
env, tl, tl, i32)
DEF_HELPER_FLAGS_3(SLBMTE, TCG_CALL_NO_RWG, void, env, tl, tl)
-DEF_HELPER_2(load_slb_esid, tl, env, tl)
+DEF_HELPER_2(SLBMFEE, tl, env, tl)
DEF_HELPER_2(SLBMFEV, tl, env, tl)
DEF_HELPER_2(find_slb_vsid, tl, env, tl)
DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index c0239335a1..22614ee915 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -803,6 +803,7 @@ SLBIA 011111 --... ----- ----- 0111110010 - @X_ih
SLBMTE 011111 ..... ----- ..... 0110010010 - @X_tb
SLBMFEV 011111 ..... ----- ..... 1101010011 - @X_tb
+SLBMFEE 011111 ..... ----- ..... 1110010011 - @X_tb
## TLB Management Instructions
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 7854b91043..5d73d64436 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -319,7 +319,7 @@ void helper_SLBMTE(CPUPPCState *env, target_ulong rb, target_ulong rs)
}
}
-target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
+target_ulong helper_SLBMFEE(CPUPPCState *env, target_ulong rb)
{
PowerPCCPU *cpu = env_archcpu(env);
target_ulong rt = 0;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index f0fc375b0c..dc87316ce7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5351,18 +5351,6 @@ static void gen_mtsrin_64b(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-static void gen_slbmfee(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV(ctx);
-#else
- CHK_SV(ctx);
-
- gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
- cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
static void gen_slbfee_(DisasContext *ctx)
{
@@ -6833,7 +6821,6 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
PPC_SEGMENT_64B),
-GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
#endif
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc
index a037fc2b95..b169bd6317 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -91,6 +91,20 @@ static bool trans_SLBMFEV(DisasContext *ctx, arg_SLBMFEV *a)
return true;
}
+static bool trans_SLBMFEE(DisasContext *ctx, arg_SLBMFEE *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+ REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+ gen_helper_SLBMFEE(cpu_gpr[a->rt], cpu_env, cpu_gpr[a->rb]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 09/11] target/ppc: Move slbfee to decodetree
2022-06-15 19:19 [PATCH 00/11] target/ppc: Implement slbiag move slb* to decodetree Lucas Coutinho
` (7 preceding siblings ...)
2022-06-15 19:20 ` [PATCH 08/11] target/ppc: Move slbmfee " Lucas Coutinho
@ 2022-06-15 19:20 ` Lucas Coutinho
2022-06-21 16:54 ` Leandro Lupori
2022-06-15 19:20 ` [PATCH 10/11] target/ppc: Move slbsync " Lucas Coutinho
` (2 subsequent siblings)
11 siblings, 1 reply; 24+ messages in thread
From: Lucas Coutinho @ 2022-06-15 19:20 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, Lucas Coutinho
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 2 ++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 26 ---------------
target/ppc/translate/storage-ctrl-impl.c.inc | 34 ++++++++++++++++++++
5 files changed, 38 insertions(+), 28 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 271dd585e0..de7bf9f175 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -685,7 +685,7 @@ DEF_HELPER_FLAGS_4(tlbie_isa300, TCG_CALL_NO_WG, void, \
DEF_HELPER_FLAGS_3(SLBMTE, TCG_CALL_NO_RWG, void, env, tl, tl)
DEF_HELPER_2(SLBMFEE, tl, env, tl)
DEF_HELPER_2(SLBMFEV, tl, env, tl)
-DEF_HELPER_2(find_slb_vsid, tl, env, tl)
+DEF_HELPER_2(SLBFEE, tl, env, tl)
DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 22614ee915..34f0e3cbeb 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -805,6 +805,8 @@ SLBMTE 011111 ..... ----- ..... 0110010010 - @X_tb
SLBMFEV 011111 ..... ----- ..... 1101010011 - @X_tb
SLBMFEE 011111 ..... ----- ..... 1110010011 - @X_tb
+SLBFEE 011111 ..... ----- ..... 1111010011 1 @X_tb
+
## TLB Management Instructions
&X_tlbie rb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 5d73d64436..7ec7a67a78 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -331,7 +331,7 @@ target_ulong helper_SLBMFEE(CPUPPCState *env, target_ulong rb)
return rt;
}
-target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb)
+target_ulong helper_SLBFEE(CPUPPCState *env, target_ulong rb)
{
PowerPCCPU *cpu = env_archcpu(env);
target_ulong rt = 0;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index dc87316ce7..62f3c19e6a 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5351,31 +5351,6 @@ static void gen_mtsrin_64b(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-
-static void gen_slbfee_(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
-#else
- TCGLabel *l1, *l2;
-
- if (unlikely(ctx->pr)) {
- gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
- return;
- }
- gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
- cpu_gpr[rB(ctx->opcode)]);
- l1 = gen_new_label();
- l2 = gen_new_label();
- tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
- tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
- tcg_gen_br(l2);
- gen_set_label(l1);
- tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
- gen_set_label(l2);
-#endif
-}
#endif /* defined(TARGET_PPC64) */
/*** Lookaside buffer management ***/
@@ -6821,7 +6796,6 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
PPC_SEGMENT_64B),
-GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
#endif
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
/*
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc
index b169bd6317..260bce35ac 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -105,6 +105,40 @@ static bool trans_SLBMFEE(DisasContext *ctx, arg_SLBMFEE *a)
return true;
}
+static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+
+#if defined(CONFIG_USER_ONLY)
+ gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
+#else
+
+#if defined(TARGET_PPC64)
+ TCGLabel *l1, *l2;
+
+ if (unlikely(ctx->pr)) {
+ gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
+ return true;
+ }
+ gen_helper_SLBFEE(cpu_gpr[a->rt], cpu_env,
+ cpu_gpr[a->rb]);
+ l1 = gen_new_label();
+ l2 = gen_new_label();
+ tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], -1, l1);
+ tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
+ tcg_gen_br(l2);
+ gen_set_label(l1);
+ tcg_gen_movi_tl(cpu_gpr[a->rt], 0);
+ gen_set_label(l2);
+#else
+ qemu_build_not_reached();
+#endif
+#endif
+ return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 10/11] target/ppc: Move slbsync to decodetree
2022-06-15 19:19 [PATCH 00/11] target/ppc: Implement slbiag move slb* to decodetree Lucas Coutinho
` (8 preceding siblings ...)
2022-06-15 19:20 ` [PATCH 09/11] target/ppc: Move slbfee " Lucas Coutinho
@ 2022-06-15 19:20 ` Lucas Coutinho
2022-06-21 16:55 ` Leandro Lupori
2022-06-15 19:20 ` [PATCH 11/11] target/ppc: Implement slbiag Lucas Coutinho
2022-06-23 22:28 ` [PATCH 00/11] target/ppc: Implement slbiag move slb* to decodetree Daniel Henrique Barboza
11 siblings, 1 reply; 24+ messages in thread
From: Lucas Coutinho @ 2022-06-15 19:20 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, Lucas Coutinho
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
---
target/ppc/insn32.decode | 2 ++
target/ppc/translate.c | 17 -----------------
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++++++++++++++
3 files changed, 16 insertions(+), 17 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 34f0e3cbeb..f7ebca578b 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -807,6 +807,8 @@ SLBMFEE 011111 ..... ----- ..... 1110010011 - @X_tb
SLBFEE 011111 ..... ----- ..... 1111010011 1 @X_tb
+SLBSYNC 011111 ----- ----- ----- 0101010010 -
+
## TLB Management Instructions
&X_tlbie rb rs ric prs:bool r:bool
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 62f3c19e6a..b005c15f98 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5388,20 +5388,6 @@ static void gen_tlbsync(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-#if defined(TARGET_PPC64)
-/* slbsync */
-static void gen_slbsync(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV(ctx);
-#else
- CHK_SV(ctx);
- gen_check_tlb_flush(ctx, true);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
-#endif /* defined(TARGET_PPC64) */
-
/*** External control ***/
/* Optional: */
@@ -6803,9 +6789,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
* different ISA versions
*/
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
-#if defined(TARGET_PPC64)
-GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
-#endif
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc
index 260bce35ac..c90cad10b4 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -139,6 +139,20 @@ static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE *a)
return true;
}
+static bool trans_SLBSYNC(DisasContext *ctx, arg_SLBSYNC *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+ gen_check_tlb_flush(ctx, true);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
{
#if defined(CONFIG_USER_ONLY)
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 11/11] target/ppc: Implement slbiag
2022-06-15 19:19 [PATCH 00/11] target/ppc: Implement slbiag move slb* to decodetree Lucas Coutinho
` (9 preceding siblings ...)
2022-06-15 19:20 ` [PATCH 10/11] target/ppc: Move slbsync " Lucas Coutinho
@ 2022-06-15 19:20 ` Lucas Coutinho
2022-06-21 16:56 ` Leandro Lupori
2022-06-23 22:28 ` [PATCH 00/11] target/ppc: Implement slbiag move slb* to decodetree Daniel Henrique Barboza
11 siblings, 1 reply; 24+ messages in thread
From: Lucas Coutinho @ 2022-06-15 19:20 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, Lucas Coutinho
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
---
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 4 +++
target/ppc/mmu-hash64.c | 27 ++++++++++++++++++++
target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++++++++++
4 files changed, 46 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index de7bf9f175..4287f41880 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -687,6 +687,7 @@ DEF_HELPER_2(SLBMFEE, tl, env, tl)
DEF_HELPER_2(SLBMFEV, tl, env, tl)
DEF_HELPER_2(SLBFEE, tl, env, tl)
DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
+DEF_HELPER_FLAGS_3(SLBIAG, TCG_CALL_NO_RWG, void, env, tl, i32)
DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
#endif
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index f7ebca578b..b36a093828 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -137,6 +137,9 @@
&X_rb rb
@X_rb ...... ..... ..... rb:5 .......... . &X_rb
+&X_rs_l rs l:bool
+@X_rs_l ...... rs:5 .... l:1 ..... .......... . &X_rs_l
+
&X_uim5 xt uim:uint8_t
@X_uim5 ...... ..... ..... uim:5 .......... . &X_uim5 xt=%x_xt
@@ -799,6 +802,7 @@ SLBIE 011111 ----- ----- ..... 0110110010 - @X_rb
SLBIEG 011111 ..... ----- ..... 0111010010 - @X_tb
SLBIA 011111 --... ----- ----- 0111110010 - @X_ih
+SLBIAG 011111 ..... ----. ----- 1101010010 - @X_rs_l
SLBMTE 011111 ..... ----- ..... 0110010010 - @X_tb
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 7ec7a67a78..b9b31fd276 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -173,6 +173,33 @@ void helper_SLBIA(CPUPPCState *env, uint32_t ih)
}
}
+#if defined(TARGET_PPC64)
+void helper_SLBIAG(CPUPPCState *env, target_ulong rs, uint32_t l)
+{
+ PowerPCCPU *cpu = env_archcpu(env);
+ int n;
+
+ /*
+ * slbiag must always flush all TLB (which is equivalent to ERAT in ppc
+ * architecture). Matching on SLB_ESID_V is not good enough, because slbmte
+ * can overwrite a valid SLB without flushing its lookaside information.
+ *
+ * It would be possible to keep the TLB in synch with the SLB by flushing
+ * when a valid entry is overwritten by slbmte, and therefore slbiag would
+ * not have to flush unless it evicts a valid SLB entry. However it is
+ * expected that slbmte is more common than slbiag, and slbiag is usually
+ * going to evict valid SLB entries, so that tradeoff is unlikely to be a
+ * good one.
+ */
+ env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
+
+ for (n = 0; n < cpu->hash64_opts->slb_size; n++) {
+ ppc_slb_t *slb = &env->slb[n];
+ slb->esid &= ~SLB_ESID_V;
+ }
+}
+#endif
+
static void __helper_slbie(CPUPPCState *env, target_ulong addr,
target_ulong global)
{
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc
index c90cad10b4..6a4ba4089e 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -63,6 +63,20 @@ static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a)
return true;
}
+static bool trans_SLBIAG(DisasContext *ctx, arg_SLBIAG *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+ gen_helper_SLBIAG(cpu_env, cpu_gpr[a->rs], tcg_constant_i32(a->l));
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a)
{
REQUIRE_64BIT(ctx);
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH 00/11] target/ppc: Implement slbiag move slb* to decodetree
2022-06-15 19:19 [PATCH 00/11] target/ppc: Implement slbiag move slb* to decodetree Lucas Coutinho
` (10 preceding siblings ...)
2022-06-15 19:20 ` [PATCH 11/11] target/ppc: Implement slbiag Lucas Coutinho
@ 2022-06-23 22:28 ` Daniel Henrique Barboza
11 siblings, 0 replies; 24+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-23 22:28 UTC (permalink / raw)
To: Lucas Coutinho, qemu-devel, qemu-ppc; +Cc: clg, david, groug, richard.henderson
Lucas,
Can you please rebase this series with current master?
I got a conflict in patch 03, and every other patch that tries to add
instructions in insn32.decode, because of a missing "TLB Management
Instructions" that are not present there anymore.
Thanks,
Daniel
On 6/15/22 16:19, Lucas Coutinho wrote:
> Implement the following PowerISA v3.0 instuction:
> slbiag: SLB Invalidate All Global X-form
>
> Move the following PowerISA v3.0 instuction to decodetree:
> slbie: SLB Invalidate Entry X-form
> slbieg: SLB Invalidate Entry Global X-form
> slbia: SLB Invalidate All X-form
> slbmte: SLB Move To Entry X-form
> slbmfev: SLB Move From Entry VSID X-form
> slbmfee: SLB Move From Entry ESID X-form
> slbfee: SLB Find Entry ESID
> slbsync: SLB Synchronize
>
> Based-on: <20220614163018.39819-1-leandro.lupori@eldorado.org.br>
>
> Lucas Coutinho (9):
> target/ppc: Move slbie to decodetree
> target/ppc: Move slbieg to decodetree
> target/ppc: Move slbia to decodetree
> target/ppc: Move slbmte to decodetree
> target/ppc: Move slbmfev to decodetree
> target/ppc: Move slbmfee to decodetree
> target/ppc: Move slbfee to decodetree
> target/ppc: Move slbsync to decodetree
> target/ppc: Implement slbiag
>
> Matheus Ferst (2):
> target/ppc: receive DisasContext explicitly in GEN_PRIV
> target/ppc: add macros to check privilege level
>
> target/ppc/helper.h | 15 +-
> target/ppc/insn32.decode | 26 ++
> target/ppc/mmu-hash64.c | 41 +-
> target/ppc/translate.c | 417 +++++++------------
> target/ppc/translate/fixedpoint-impl.c.inc | 7 +-
> target/ppc/translate/fp-impl.c.inc | 4 +-
> target/ppc/translate/storage-ctrl-impl.c.inc | 146 +++++++
> 7 files changed, 377 insertions(+), 279 deletions(-)
>
^ permalink raw reply [flat|nested] 24+ messages in thread