From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1J2Gae-0002g3-8D for qemu-devel@nongnu.org; Tue, 11 Dec 2007 20:40:48 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1J2Gac-0002ew-L7 for qemu-devel@nongnu.org; Tue, 11 Dec 2007 20:40:47 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1J2Gac-0002ep-Gf for qemu-devel@nongnu.org; Tue, 11 Dec 2007 20:40:46 -0500 Received: from an-out-0708.google.com ([209.85.132.242]) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1J2Gac-0000rB-9Z for qemu-devel@nongnu.org; Tue, 11 Dec 2007 20:40:46 -0500 Received: by an-out-0708.google.com with SMTP id b38so10714ana.130 for ; Tue, 11 Dec 2007 17:40:45 -0800 (PST) Message-ID: <475F3C1B.707@codemonkey.ws> Date: Tue, 11 Dec 2007 19:40:43 -0600 From: Anthony Liguori MIME-Version: 1.0 Subject: Re: [Qemu-devel] Re: [PATCH 2/3] virtio network device References: <4755CC8C.6000001@us.ibm.com> <20071208215510.GB30486@shareable.org> <475B1488.5040200@codemonkey.ws> <200712121224.38403.rusty@rustcorp.com.au> In-Reply-To: <200712121224.38403.rusty@rustcorp.com.au> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Rusty Russell Cc: Anthony Liguori , qemu-devel@nongnu.org, Paul Brook Rusty Russell wrote: > On Sunday 09 December 2007 09:02:48 Anthony Liguori wrote: > >> If QEMU ever got true SMP support, then virtio would not work as it >> requires 16-bit atomic writes which AFAIK is not possible on a number of >> non-x86 architectures. >> > > Hmm? Where is this requirement coming from? > > I think everyone should stop using the word "atomic" in virtio discussions; > it's confusing. > The virtio ring queue indices are 16-bit and are readable to one end while writable on the other end. To ensure that this can be done in a lock-less way, it's necessary to atomically update the index. Atomic is the right word here because if the 16-bit write gets converted into two 8-bit writes, then very bad things could happen with SMP. Regards, Anthony Liguori > Rusty. > >