From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43)
	id 1J2jsd-0004dB-Em
	for qemu-devel@nongnu.org; Thu, 13 Dec 2007 03:57:19 -0500
Received: from [199.232.76.173] (helo=monty-python.gnu.org)
	by lists.gnu.org with esmtp (Exim 4.43) id 1J2jsc-0004av-BP
	for qemu-devel@nongnu.org; Thu, 13 Dec 2007 03:57:18 -0500
Received: from mx1.polytechnique.org ([129.104.30.34])
	by monty-python.gnu.org with esmtps
	(TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60)
	(envelope-from <fabrice@bellard.org>) id 1J2jsc-0000Ji-4p
	for qemu-devel@nongnu.org; Thu, 13 Dec 2007 03:57:18 -0500
Message-ID: <4760F3E7.9000208@bellard.org>
Date: Thu, 13 Dec 2007 09:57:11 +0100
From: Fabrice Bellard <fabrice@bellard.org>
MIME-Version: 1.0
Subject: Re: [Qemu-devel] [PATCH] arm eabi TLS
References: <1197420297.2947.94.camel@phantasm.home.enterpriseandprosperity.com>
	<476068AA.80001@bellard.org>
	<200712130121.04204.paul@codesourcery.com>
In-Reply-To: <200712130121.04204.paul@codesourcery.com>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
Content-Transfer-Encoding: 7bit
Reply-To: qemu-devel@nongnu.org
List-Id: qemu-devel.nongnu.org
List-Unsubscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.gnu.org/pipermail/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Paul Brook <paul@codesourcery.com>
Cc: qemu-devel@nongnu.org, thayne@c2.net

Paul Brook wrote:
>> - It would be good to limit the changes in the CPU emulation code to
>> handle the TLS. For example, on MIPS, the TLS register must not be
>> stored in the CPU state. Same for ARM.
> 
> I disagree. The TLS register is part of the CPU state. On many machines 
> (including ARMv6 CPUs) it's an actual CPU register. I'm fairly sure the same 
> is true for recent MIPS revisions.

If some CPUs implement it in hardware, then I agree.

Fabrice.