* [Qemu-devel] [PATCH] sparc32: add asi debug info
@ 2007-12-28 17:30 Robert Reif
0 siblings, 0 replies; only message in thread
From: Robert Reif @ 2007-12-28 17:30 UTC (permalink / raw)
To: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 29 bytes --]
Add asi debug info printing.
[-- Attachment #2: asi.diff.txt --]
[-- Type: text/plain, Size: 3666 bytes --]
diff -p -u -r1.61 op_helper.c
--- target-sparc/op_helper.c 10 Dec 2007 19:58:20 -0000 1.61
+++ target-sparc/op_helper.c 28 Dec 2007 17:23:29 -0000
@@ -6,6 +6,7 @@
//#define DEBUG_MXCC
//#define DEBUG_UNALIGNED
//#define DEBUG_UNASSIGNED
+//#define DEBUG_ASI
#ifdef DEBUG_MMU
#define DPRINTF_MMU(fmt, args...) \
@@ -21,6 +22,13 @@ do { printf("MXCC: " fmt , ##args); } wh
#define DPRINTF_MXCC(fmt, args...)
#endif
+#ifdef DEBUG_ASI
+#define DPRINTF_ASI(fmt, args...) \
+do { printf("ASI: " fmt , ##args); } while (0)
+#else
+#define DPRINTF_ASI(fmt, args...)
+#endif
+
void raise_exception(int tt)
{
env->exception_index = tt;
@@ -229,11 +237,34 @@ static void dump_mxcc(CPUState *env)
}
#endif
+#ifdef DEBUG_ASI
+static void dump_asi(const char * txt, uint32_t addr, int asi, int size,
+ uint32_t r1, uint32_t r2)
+{
+ switch (size)
+ {
+ case 1:
+ DPRINTF_ASI("%s %08x asi 0x%02x = %02x\n", txt, addr, asi, r1 & 0xff);
+ break;
+ case 2:
+ DPRINTF_ASI("%s %08x asi 0x%02x = %04x\n", txt, addr, asi, r1 & 0xffff);
+ break;
+ case 4:
+ DPRINTF_ASI("%s %08x asi 0x%02x = %08x\n", txt, addr, asi, r1);
+ break;
+ case 8:
+ DPRINTF_ASI("%s %08x asi 0x%02x = %016llx\n", txt, addr, asi,
+ r2 | ((uint64_t)r1 << 32));
+ break;
+ }
+}
+#endif
+
void helper_ld_asi(int asi, int size, int sign)
{
uint32_t ret = 0;
uint64_t tmp;
-#ifdef DEBUG_MXCC
+#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
uint32_t last_T0 = T0;
#endif
@@ -435,6 +466,10 @@ void helper_ld_asi(int asi, int size, in
}
else
T1 = ret;
+
+#ifdef DEBUG_ASI
+ dump_asi("read ", last_T0, asi, size, T1, T0);
+#endif
}
void helper_st_asi(int asi, int size)
@@ -542,8 +577,8 @@ void helper_st_asi(int asi, int size)
#ifdef DEBUG_MMU
dump_mmu(env);
#endif
- return;
}
+ break;
case 4: /* write MMU regs */
{
int reg = (T0 >> 8) & 0x1f;
@@ -587,8 +622,8 @@ void helper_st_asi(int asi, int size)
#ifdef DEBUG_MMU
dump_mmu(env);
#endif
- return;
}
+ break;
case 0xa: /* User data access */
switch(size) {
case 1:
@@ -646,7 +681,7 @@ void helper_st_asi(int asi, int size)
stl_kernel(dst, temp);
}
}
- return;
+ break;
case 0x1f: /* Block fill, stda access */
{
// value (T1, T2)
@@ -661,7 +696,7 @@ void helper_st_asi(int asi, int size)
for (i = 0; i < 32; i += 8, dst += 8)
stq_kernel(dst, val);
}
- return;
+ break;
case 0x20: /* MMU passthrough */
{
switch(size) {
@@ -680,7 +715,7 @@ void helper_st_asi(int asi, int size)
break;
}
}
- return;
+ break;
case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
{
@@ -705,7 +740,7 @@ void helper_st_asi(int asi, int size)
break;
}
}
- return;
+ break;
case 0x30: /* store buffer tags */
case 0x31: /* store buffer data or Ross RT620 I-cache flush */
case 0x32: /* store buffer control */
@@ -718,8 +753,11 @@ void helper_st_asi(int asi, int size)
case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
default:
do_unassigned_access(T0, 1, 0, 1);
- return;
+ break;
}
+#ifdef DEBUG_ASI
+ dump_asi("write", T0, asi, size, T1, T2);
+#endif
}
#endif /* CONFIG_USER_ONLY */
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