From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48683) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YwJUY-00074i-MY for qemu-devel@nongnu.org; Sat, 23 May 2015 20:10:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YwJUV-0002z0-0h for qemu-devel@nongnu.org; Sat, 23 May 2015 20:10:10 -0400 Received: from nm13-vm9.bullet.mail.tp2.yahoo.com ([203.188.200.185]:37866) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YwJUU-0002rc-Ed for qemu-devel@nongnu.org; Sat, 23 May 2015 20:10:06 -0400 Date: Sun, 24 May 2015 00:09:58 +0000 (UTC) From: =?UTF-8?B?5rWp5YCrIOmtjw==?= Message-ID: <477790825.348663.1432426198996.JavaMail.yahoo@mail.yahoo.com> In-Reply-To: References: MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_Part_348662_946802537.1432426198993" Subject: Re: [Qemu-devel] What's the differences betweencld/st and qemu_ld/st in TCG IR? Reply-To: =?UTF-8?B?5rWp5YCrIOmtjw==?= List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: "qemu-devel@nongnu.org" ------=_Part_348662_946802537.1432426198993 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Dear Peter: Now I get it, thanks for the help! :-) =20 Peter Maydell =E6=96=BC 2015/5/24 (=E9=80= =B1=E6=97=A5) 5:17 AM =E5=AF=AB=E9=81=93=EF=B9=95 =20 On 23 May 2015 at 13:18, =E6=B5=A9=E5=80=AB =E9=AD=8F wrote: > Hi, all: > I've been trying to understand the process of binary translation inside T= CG. > If I haven't misunderstood, qemu_ld/st are the operations that will call > helper function(ld_mmu) to let softmmu translate the GVA->GPA for the gue= st > load/store instructions. > So there are some points that I hope you can help me out: > 1. Is every guest load/store instruction would be translated to qemu_ld/s= t > IR? Yes, as a general rule. There are a few special cases: * sometimes complicated instructions are just translated into =C2=A0 calls to helper functions which do the guest memory access =C2=A0 at runtime (for instance x86 cmpxchg8b turns into a call to =C2=A0 helper_cmpxchg8b()) * for linux-user some of the atomic instructions (load-lock/ =C2=A0 store-conditional pairs) are handled by translating to a =C2=A0 "raise internal exception" call, and the actual load/store =C2=A0 is then dealt with in linux-user/main.c =C2=A0 [This mechanism might change in the near future; we're looking at =C2=A0 multi-threaded TCG emulation, and so might switch the linux-user =C2=A0 atomics to work the same way as a future mechanism for doing atomics =C2=A0 in multi-threaded system emulation] But almost all guest accesses will turn into qemu_ld/st ops. > 2. What about another TCG IR "ld/st"? What kind of guest instructions wou= ld > cause TCG generates that IRs and for what purpose? These just do plain load/store to the *host* address specified. This is almost always used to read a value from the CPU state structure (CPUARMState, etc). Generated code always has access to a pointer to this struct, and uses the ld/st ops to read or write fields within it. (If you search for tcg_gen_ld in target-*/ you'll see lots of examples.) The op can be used for any host load or store, but in practice use for anything other than "read a value from the CPU state struct" is very rare. -- PMM ------=_Part_348662_946802537.1432426198993 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
Dear Peter:

Now I get it, thanks for the help! :-)



Peter Maydell <peter.maydell@linaro.org> =E6=96=BC 20= 15/5/24 (=E9=80=B1=E6=97=A5) 5:17 AM =E5=AF=AB=E9=81=93=EF=B9=95


On 23 May 2015 at 13:18, = =E6=B5=A9=E5=80=AB =E9=AD=8F <goberwei@yahoo.com.t= w> wrote:
> Hi, all:
> I'v= e been trying to understand the process of binary translation inside TCG.> If I haven't misunderstood, qemu_ld/st are the operat= ions that will call
> helper function(ld_mmu) to let s= oftmmu translate the GVA->GPA for the guest
> load/= store instructions.
> So there are some points that I = hope you can help me out:
> 1. Is every guest load/sto= re instruction would be translated to qemu_ld/st
> IR?=

Yes, as a general rule. There are a f= ew special cases:
* sometimes complicated instructions a= re just translated into
  calls to helper functions= which do the guest memory access
  at runtime (for= instance x86 cmpxchg8b turns into a call to
  help= er_cmpxchg8b())
* for linux-user some of the atomic inst= ructions (load-lock/
  store-conditional pairs) are= handled by translating to a
  "raise internal exce= ption" call, and the actual load/store
  is then de= alt with in linux-user/main.c
  [This mechanism mig= ht change in the near future; we're looking at
  mu= lti-threaded TCG emulation, and so might switch the linux-user
  atomics to work the same way as a future mechanism for doing = atomics
  in multi-threaded system emulation]
But almost all guest accesses will turn into qemu_ld/st ops.

> 2. What about another TCG IR "ld/st"? What kind of guest ins= tructions would
> cause TCG generates that IRs and for= what purpose?


These just do pla= in load/store to the *host* address specified.
This is al= most always used to read a value from the CPU state
struc= ture (CPUARMState, etc). Generated code always has access
to a pointer to this struct, and uses the ld/st ops to read
or write fields within it. (If you search for tcg_gen_ld
in target-*/ you'll see lots of examples.) The op can be used
for any host load or store, but in practice use for anything
other than "read a value from the CPU state struct" is very r= are.

-- PMM



=
------=_Part_348662_946802537.1432426198993--